/******************************************************************************
*
* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/

#ifndef _IPI_H_
#define _IPI_H_

#ifdef __cplusplus
extern "C" {
#endif

/**
 * IPI Base Address
 */
#define IPI_BASEADDR      ((u32)0XFF300000U)

/**
 * Register: IPI_APU_TRIG
 */
#define IPI_APU_TRIG    ( ( IPI_BASEADDR ) + ((u32)0X00000000U) )

#define IPI_APU_TRIG_PL_3_SHIFT   27
#define IPI_APU_TRIG_PL_3_WIDTH   1
#define IPI_APU_TRIG_PL_3_MASK    ((u32)0X08000000U)

#define IPI_APU_TRIG_PL_2_SHIFT   26
#define IPI_APU_TRIG_PL_2_WIDTH   1
#define IPI_APU_TRIG_PL_2_MASK    ((u32)0X04000000U)

#define IPI_APU_TRIG_PL_1_SHIFT   25
#define IPI_APU_TRIG_PL_1_WIDTH   1
#define IPI_APU_TRIG_PL_1_MASK    ((u32)0X02000000U)

#define IPI_APU_TRIG_PL_0_SHIFT   24
#define IPI_APU_TRIG_PL_0_WIDTH   1
#define IPI_APU_TRIG_PL_0_MASK    ((u32)0X01000000U)

#define IPI_APU_TRIG_PMU_3_SHIFT   19
#define IPI_APU_TRIG_PMU_3_WIDTH   1
#define IPI_APU_TRIG_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_APU_TRIG_PMU_2_SHIFT   18
#define IPI_APU_TRIG_PMU_2_WIDTH   1
#define IPI_APU_TRIG_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_APU_TRIG_PMU_1_SHIFT   17
#define IPI_APU_TRIG_PMU_1_WIDTH   1
#define IPI_APU_TRIG_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_APU_TRIG_PMU_0_SHIFT   16
#define IPI_APU_TRIG_PMU_0_WIDTH   1
#define IPI_APU_TRIG_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_APU_TRIG_RPU_1_SHIFT   9
#define IPI_APU_TRIG_RPU_1_WIDTH   1
#define IPI_APU_TRIG_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_APU_TRIG_RPU_0_SHIFT   8
#define IPI_APU_TRIG_RPU_0_WIDTH   1
#define IPI_APU_TRIG_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_APU_TRIG_APU_SHIFT   0
#define IPI_APU_TRIG_APU_WIDTH   1
#define IPI_APU_TRIG_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_APU_OBS
 */
#define IPI_APU_OBS    ( ( IPI_BASEADDR ) + ((u32)0X00000004U) )

#define IPI_APU_OBS_PL_3_SHIFT   27
#define IPI_APU_OBS_PL_3_WIDTH   1
#define IPI_APU_OBS_PL_3_MASK    ((u32)0X08000000U)

#define IPI_APU_OBS_PL_2_SHIFT   26
#define IPI_APU_OBS_PL_2_WIDTH   1
#define IPI_APU_OBS_PL_2_MASK    ((u32)0X04000000U)

#define IPI_APU_OBS_PL_1_SHIFT   25
#define IPI_APU_OBS_PL_1_WIDTH   1
#define IPI_APU_OBS_PL_1_MASK    ((u32)0X02000000U)

#define IPI_APU_OBS_PL_0_SHIFT   24
#define IPI_APU_OBS_PL_0_WIDTH   1
#define IPI_APU_OBS_PL_0_MASK    ((u32)0X01000000U)

#define IPI_APU_OBS_PMU_3_SHIFT   19
#define IPI_APU_OBS_PMU_3_WIDTH   1
#define IPI_APU_OBS_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_APU_OBS_PMU_2_SHIFT   18
#define IPI_APU_OBS_PMU_2_WIDTH   1
#define IPI_APU_OBS_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_APU_OBS_PMU_1_SHIFT   17
#define IPI_APU_OBS_PMU_1_WIDTH   1
#define IPI_APU_OBS_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_APU_OBS_PMU_0_SHIFT   16
#define IPI_APU_OBS_PMU_0_WIDTH   1
#define IPI_APU_OBS_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_APU_OBS_RPU_1_SHIFT   9
#define IPI_APU_OBS_RPU_1_WIDTH   1
#define IPI_APU_OBS_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_APU_OBS_RPU_0_SHIFT   8
#define IPI_APU_OBS_RPU_0_WIDTH   1
#define IPI_APU_OBS_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_APU_OBS_APU_SHIFT   0
#define IPI_APU_OBS_APU_WIDTH   1
#define IPI_APU_OBS_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_APU_ISR
 */
#define IPI_APU_ISR    ( ( IPI_BASEADDR ) + ((u32)0X00000010U) )

#define IPI_APU_ISR_PL_3_SHIFT   27
#define IPI_APU_ISR_PL_3_WIDTH   1
#define IPI_APU_ISR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_APU_ISR_PL_2_SHIFT   26
#define IPI_APU_ISR_PL_2_WIDTH   1
#define IPI_APU_ISR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_APU_ISR_PL_1_SHIFT   25
#define IPI_APU_ISR_PL_1_WIDTH   1
#define IPI_APU_ISR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_APU_ISR_PL_0_SHIFT   24
#define IPI_APU_ISR_PL_0_WIDTH   1
#define IPI_APU_ISR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_APU_ISR_PMU_3_SHIFT   19
#define IPI_APU_ISR_PMU_3_WIDTH   1
#define IPI_APU_ISR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_APU_ISR_PMU_2_SHIFT   18
#define IPI_APU_ISR_PMU_2_WIDTH   1
#define IPI_APU_ISR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_APU_ISR_PMU_1_SHIFT   17
#define IPI_APU_ISR_PMU_1_WIDTH   1
#define IPI_APU_ISR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_APU_ISR_PMU_0_SHIFT   16
#define IPI_APU_ISR_PMU_0_WIDTH   1
#define IPI_APU_ISR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_APU_ISR_RPU_1_SHIFT   9
#define IPI_APU_ISR_RPU_1_WIDTH   1
#define IPI_APU_ISR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_APU_ISR_RPU_0_SHIFT   8
#define IPI_APU_ISR_RPU_0_WIDTH   1
#define IPI_APU_ISR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_APU_ISR_APU_SHIFT   0
#define IPI_APU_ISR_APU_WIDTH   1
#define IPI_APU_ISR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_APU_IMR
 */
#define IPI_APU_IMR    ( ( IPI_BASEADDR ) + ((u32)0X00000014U) )

#define IPI_APU_IMR_PL_3_SHIFT   27
#define IPI_APU_IMR_PL_3_WIDTH   1
#define IPI_APU_IMR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_APU_IMR_PL_2_SHIFT   26
#define IPI_APU_IMR_PL_2_WIDTH   1
#define IPI_APU_IMR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_APU_IMR_PL_1_SHIFT   25
#define IPI_APU_IMR_PL_1_WIDTH   1
#define IPI_APU_IMR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_APU_IMR_PL_0_SHIFT   24
#define IPI_APU_IMR_PL_0_WIDTH   1
#define IPI_APU_IMR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_APU_IMR_PMU_3_SHIFT   19
#define IPI_APU_IMR_PMU_3_WIDTH   1
#define IPI_APU_IMR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_APU_IMR_PMU_2_SHIFT   18
#define IPI_APU_IMR_PMU_2_WIDTH   1
#define IPI_APU_IMR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_APU_IMR_PMU_1_SHIFT   17
#define IPI_APU_IMR_PMU_1_WIDTH   1
#define IPI_APU_IMR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_APU_IMR_PMU_0_SHIFT   16
#define IPI_APU_IMR_PMU_0_WIDTH   1
#define IPI_APU_IMR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_APU_IMR_RPU_1_SHIFT   9
#define IPI_APU_IMR_RPU_1_WIDTH   1
#define IPI_APU_IMR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_APU_IMR_RPU_0_SHIFT   8
#define IPI_APU_IMR_RPU_0_WIDTH   1
#define IPI_APU_IMR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_APU_IMR_APU_SHIFT   0
#define IPI_APU_IMR_APU_WIDTH   1
#define IPI_APU_IMR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_APU_IER
 */
#define IPI_APU_IER    ( ( IPI_BASEADDR ) + ((u32)0X00000018U) )

#define IPI_APU_IER_PL_3_SHIFT   27
#define IPI_APU_IER_PL_3_WIDTH   1
#define IPI_APU_IER_PL_3_MASK    ((u32)0X08000000U)

#define IPI_APU_IER_PL_2_SHIFT   26
#define IPI_APU_IER_PL_2_WIDTH   1
#define IPI_APU_IER_PL_2_MASK    ((u32)0X04000000U)

#define IPI_APU_IER_PL_1_SHIFT   25
#define IPI_APU_IER_PL_1_WIDTH   1
#define IPI_APU_IER_PL_1_MASK    ((u32)0X02000000U)

#define IPI_APU_IER_PL_0_SHIFT   24
#define IPI_APU_IER_PL_0_WIDTH   1
#define IPI_APU_IER_PL_0_MASK    ((u32)0X01000000U)

#define IPI_APU_IER_PMU_3_SHIFT   19
#define IPI_APU_IER_PMU_3_WIDTH   1
#define IPI_APU_IER_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_APU_IER_PMU_2_SHIFT   18
#define IPI_APU_IER_PMU_2_WIDTH   1
#define IPI_APU_IER_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_APU_IER_PMU_1_SHIFT   17
#define IPI_APU_IER_PMU_1_WIDTH   1
#define IPI_APU_IER_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_APU_IER_PMU_0_SHIFT   16
#define IPI_APU_IER_PMU_0_WIDTH   1
#define IPI_APU_IER_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_APU_IER_RPU_1_SHIFT   9
#define IPI_APU_IER_RPU_1_WIDTH   1
#define IPI_APU_IER_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_APU_IER_RPU_0_SHIFT   8
#define IPI_APU_IER_RPU_0_WIDTH   1
#define IPI_APU_IER_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_APU_IER_APU_SHIFT   0
#define IPI_APU_IER_APU_WIDTH   1
#define IPI_APU_IER_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_APU_IDR
 */
#define IPI_APU_IDR    ( ( IPI_BASEADDR ) + ((u32)0X0000001CU) )

#define IPI_APU_IDR_PL_3_SHIFT   27
#define IPI_APU_IDR_PL_3_WIDTH   1
#define IPI_APU_IDR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_APU_IDR_PL_2_SHIFT   26
#define IPI_APU_IDR_PL_2_WIDTH   1
#define IPI_APU_IDR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_APU_IDR_PL_1_SHIFT   25
#define IPI_APU_IDR_PL_1_WIDTH   1
#define IPI_APU_IDR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_APU_IDR_PL_0_SHIFT   24
#define IPI_APU_IDR_PL_0_WIDTH   1
#define IPI_APU_IDR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_APU_IDR_PMU_3_SHIFT   19
#define IPI_APU_IDR_PMU_3_WIDTH   1
#define IPI_APU_IDR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_APU_IDR_PMU_2_SHIFT   18
#define IPI_APU_IDR_PMU_2_WIDTH   1
#define IPI_APU_IDR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_APU_IDR_PMU_1_SHIFT   17
#define IPI_APU_IDR_PMU_1_WIDTH   1
#define IPI_APU_IDR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_APU_IDR_PMU_0_SHIFT   16
#define IPI_APU_IDR_PMU_0_WIDTH   1
#define IPI_APU_IDR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_APU_IDR_RPU_1_SHIFT   9
#define IPI_APU_IDR_RPU_1_WIDTH   1
#define IPI_APU_IDR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_APU_IDR_RPU_0_SHIFT   8
#define IPI_APU_IDR_RPU_0_WIDTH   1
#define IPI_APU_IDR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_APU_IDR_APU_SHIFT   0
#define IPI_APU_IDR_APU_WIDTH   1
#define IPI_APU_IDR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_RPU_0_TRIG
 */
#define IPI_RPU_0_TRIG    ( ( IPI_BASEADDR ) + ((u32)0X00010000U) )

#define IPI_RPU_0_TRIG_PL_3_SHIFT   27
#define IPI_RPU_0_TRIG_PL_3_WIDTH   1
#define IPI_RPU_0_TRIG_PL_3_MASK    ((u32)0X08000000U)

#define IPI_RPU_0_TRIG_PL_2_SHIFT   26
#define IPI_RPU_0_TRIG_PL_2_WIDTH   1
#define IPI_RPU_0_TRIG_PL_2_MASK    ((u32)0X04000000U)

#define IPI_RPU_0_TRIG_PL_1_SHIFT   25
#define IPI_RPU_0_TRIG_PL_1_WIDTH   1
#define IPI_RPU_0_TRIG_PL_1_MASK    ((u32)0X02000000U)

#define IPI_RPU_0_TRIG_PL_0_SHIFT   24
#define IPI_RPU_0_TRIG_PL_0_WIDTH   1
#define IPI_RPU_0_TRIG_PL_0_MASK    ((u32)0X01000000U)

#define IPI_RPU_0_TRIG_PMU_3_SHIFT   19
#define IPI_RPU_0_TRIG_PMU_3_WIDTH   1
#define IPI_RPU_0_TRIG_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_RPU_0_TRIG_PMU_2_SHIFT   18
#define IPI_RPU_0_TRIG_PMU_2_WIDTH   1
#define IPI_RPU_0_TRIG_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_RPU_0_TRIG_PMU_1_SHIFT   17
#define IPI_RPU_0_TRIG_PMU_1_WIDTH   1
#define IPI_RPU_0_TRIG_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_RPU_0_TRIG_PMU_0_SHIFT   16
#define IPI_RPU_0_TRIG_PMU_0_WIDTH   1
#define IPI_RPU_0_TRIG_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_RPU_0_TRIG_RPU_1_SHIFT   9
#define IPI_RPU_0_TRIG_RPU_1_WIDTH   1
#define IPI_RPU_0_TRIG_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_RPU_0_TRIG_RPU_0_SHIFT   8
#define IPI_RPU_0_TRIG_RPU_0_WIDTH   1
#define IPI_RPU_0_TRIG_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_RPU_0_TRIG_APU_SHIFT   0
#define IPI_RPU_0_TRIG_APU_WIDTH   1
#define IPI_RPU_0_TRIG_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_RPU_0_OBS
 */
#define IPI_RPU_0_OBS    ( ( IPI_BASEADDR ) + ((u32)0X00010004U) )

#define IPI_RPU_0_OBS_PL_3_SHIFT   27
#define IPI_RPU_0_OBS_PL_3_WIDTH   1
#define IPI_RPU_0_OBS_PL_3_MASK    ((u32)0X08000000U)

#define IPI_RPU_0_OBS_PL_2_SHIFT   26
#define IPI_RPU_0_OBS_PL_2_WIDTH   1
#define IPI_RPU_0_OBS_PL_2_MASK    ((u32)0X04000000U)

#define IPI_RPU_0_OBS_PL_1_SHIFT   25
#define IPI_RPU_0_OBS_PL_1_WIDTH   1
#define IPI_RPU_0_OBS_PL_1_MASK    ((u32)0X02000000U)

#define IPI_RPU_0_OBS_PL_0_SHIFT   24
#define IPI_RPU_0_OBS_PL_0_WIDTH   1
#define IPI_RPU_0_OBS_PL_0_MASK    ((u32)0X01000000U)

#define IPI_RPU_0_OBS_PMU_3_SHIFT   19
#define IPI_RPU_0_OBS_PMU_3_WIDTH   1
#define IPI_RPU_0_OBS_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_RPU_0_OBS_PMU_2_SHIFT   18
#define IPI_RPU_0_OBS_PMU_2_WIDTH   1
#define IPI_RPU_0_OBS_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_RPU_0_OBS_PMU_1_SHIFT   17
#define IPI_RPU_0_OBS_PMU_1_WIDTH   1
#define IPI_RPU_0_OBS_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_RPU_0_OBS_PMU_0_SHIFT   16
#define IPI_RPU_0_OBS_PMU_0_WIDTH   1
#define IPI_RPU_0_OBS_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_RPU_0_OBS_RPU_1_SHIFT   9
#define IPI_RPU_0_OBS_RPU_1_WIDTH   1
#define IPI_RPU_0_OBS_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_RPU_0_OBS_RPU_0_SHIFT   8
#define IPI_RPU_0_OBS_RPU_0_WIDTH   1
#define IPI_RPU_0_OBS_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_RPU_0_OBS_APU_SHIFT   0
#define IPI_RPU_0_OBS_APU_WIDTH   1
#define IPI_RPU_0_OBS_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_RPU_0_ISR
 */
#define IPI_RPU_0_ISR    ( ( IPI_BASEADDR ) + ((u32)0X00010010U) )

#define IPI_RPU_0_ISR_PL_3_SHIFT   27
#define IPI_RPU_0_ISR_PL_3_WIDTH   1
#define IPI_RPU_0_ISR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_RPU_0_ISR_PL_2_SHIFT   26
#define IPI_RPU_0_ISR_PL_2_WIDTH   1
#define IPI_RPU_0_ISR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_RPU_0_ISR_PL_1_SHIFT   25
#define IPI_RPU_0_ISR_PL_1_WIDTH   1
#define IPI_RPU_0_ISR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_RPU_0_ISR_PL_0_SHIFT   24
#define IPI_RPU_0_ISR_PL_0_WIDTH   1
#define IPI_RPU_0_ISR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_RPU_0_ISR_PMU_3_SHIFT   19
#define IPI_RPU_0_ISR_PMU_3_WIDTH   1
#define IPI_RPU_0_ISR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_RPU_0_ISR_PMU_2_SHIFT   18
#define IPI_RPU_0_ISR_PMU_2_WIDTH   1
#define IPI_RPU_0_ISR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_RPU_0_ISR_PMU_1_SHIFT   17
#define IPI_RPU_0_ISR_PMU_1_WIDTH   1
#define IPI_RPU_0_ISR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_RPU_0_ISR_PMU_0_SHIFT   16
#define IPI_RPU_0_ISR_PMU_0_WIDTH   1
#define IPI_RPU_0_ISR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_RPU_0_ISR_RPU_1_SHIFT   9
#define IPI_RPU_0_ISR_RPU_1_WIDTH   1
#define IPI_RPU_0_ISR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_RPU_0_ISR_RPU_0_SHIFT   8
#define IPI_RPU_0_ISR_RPU_0_WIDTH   1
#define IPI_RPU_0_ISR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_RPU_0_ISR_APU_SHIFT   0
#define IPI_RPU_0_ISR_APU_WIDTH   1
#define IPI_RPU_0_ISR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_RPU_0_IMR
 */
#define IPI_RPU_0_IMR    ( ( IPI_BASEADDR ) + ((u32)0X00010014U) )

#define IPI_RPU_0_IMR_PL_3_SHIFT   27
#define IPI_RPU_0_IMR_PL_3_WIDTH   1
#define IPI_RPU_0_IMR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_RPU_0_IMR_PL_2_SHIFT   26
#define IPI_RPU_0_IMR_PL_2_WIDTH   1
#define IPI_RPU_0_IMR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_RPU_0_IMR_PL_1_SHIFT   25
#define IPI_RPU_0_IMR_PL_1_WIDTH   1
#define IPI_RPU_0_IMR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_RPU_0_IMR_PL_0_SHIFT   24
#define IPI_RPU_0_IMR_PL_0_WIDTH   1
#define IPI_RPU_0_IMR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_RPU_0_IMR_PMU_3_SHIFT   19
#define IPI_RPU_0_IMR_PMU_3_WIDTH   1
#define IPI_RPU_0_IMR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_RPU_0_IMR_PMU_2_SHIFT   18
#define IPI_RPU_0_IMR_PMU_2_WIDTH   1
#define IPI_RPU_0_IMR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_RPU_0_IMR_PMU_1_SHIFT   17
#define IPI_RPU_0_IMR_PMU_1_WIDTH   1
#define IPI_RPU_0_IMR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_RPU_0_IMR_PMU_0_SHIFT   16
#define IPI_RPU_0_IMR_PMU_0_WIDTH   1
#define IPI_RPU_0_IMR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_RPU_0_IMR_RPU_1_SHIFT   9
#define IPI_RPU_0_IMR_RPU_1_WIDTH   1
#define IPI_RPU_0_IMR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_RPU_0_IMR_RPU_0_SHIFT   8
#define IPI_RPU_0_IMR_RPU_0_WIDTH   1
#define IPI_RPU_0_IMR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_RPU_0_IMR_APU_SHIFT   0
#define IPI_RPU_0_IMR_APU_WIDTH   1
#define IPI_RPU_0_IMR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_RPU_0_IER
 */
#define IPI_RPU_0_IER    ( ( IPI_BASEADDR ) + ((u32)0X00010018U) )

#define IPI_RPU_0_IER_PL_3_SHIFT   27
#define IPI_RPU_0_IER_PL_3_WIDTH   1
#define IPI_RPU_0_IER_PL_3_MASK    ((u32)0X08000000U)

#define IPI_RPU_0_IER_PL_2_SHIFT   26
#define IPI_RPU_0_IER_PL_2_WIDTH   1
#define IPI_RPU_0_IER_PL_2_MASK    ((u32)0X04000000U)

#define IPI_RPU_0_IER_PL_1_SHIFT   25
#define IPI_RPU_0_IER_PL_1_WIDTH   1
#define IPI_RPU_0_IER_PL_1_MASK    ((u32)0X02000000U)

#define IPI_RPU_0_IER_PL_0_SHIFT   24
#define IPI_RPU_0_IER_PL_0_WIDTH   1
#define IPI_RPU_0_IER_PL_0_MASK    ((u32)0X01000000U)

#define IPI_RPU_0_IER_PMU_3_SHIFT   19
#define IPI_RPU_0_IER_PMU_3_WIDTH   1
#define IPI_RPU_0_IER_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_RPU_0_IER_PMU_2_SHIFT   18
#define IPI_RPU_0_IER_PMU_2_WIDTH   1
#define IPI_RPU_0_IER_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_RPU_0_IER_PMU_1_SHIFT   17
#define IPI_RPU_0_IER_PMU_1_WIDTH   1
#define IPI_RPU_0_IER_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_RPU_0_IER_PMU_0_SHIFT   16
#define IPI_RPU_0_IER_PMU_0_WIDTH   1
#define IPI_RPU_0_IER_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_RPU_0_IER_RPU_1_SHIFT   9
#define IPI_RPU_0_IER_RPU_1_WIDTH   1
#define IPI_RPU_0_IER_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_RPU_0_IER_RPU_0_SHIFT   8
#define IPI_RPU_0_IER_RPU_0_WIDTH   1
#define IPI_RPU_0_IER_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_RPU_0_IER_APU_SHIFT   0
#define IPI_RPU_0_IER_APU_WIDTH   1
#define IPI_RPU_0_IER_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_RPU_0_IDR
 */
#define IPI_RPU_0_IDR    ( ( IPI_BASEADDR ) + ((u32)0X0001001CU) )

#define IPI_RPU_0_IDR_PL_3_SHIFT   27
#define IPI_RPU_0_IDR_PL_3_WIDTH   1
#define IPI_RPU_0_IDR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_RPU_0_IDR_PL_2_SHIFT   26
#define IPI_RPU_0_IDR_PL_2_WIDTH   1
#define IPI_RPU_0_IDR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_RPU_0_IDR_PL_1_SHIFT   25
#define IPI_RPU_0_IDR_PL_1_WIDTH   1
#define IPI_RPU_0_IDR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_RPU_0_IDR_PL_0_SHIFT   24
#define IPI_RPU_0_IDR_PL_0_WIDTH   1
#define IPI_RPU_0_IDR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_RPU_0_IDR_PMU_3_SHIFT   19
#define IPI_RPU_0_IDR_PMU_3_WIDTH   1
#define IPI_RPU_0_IDR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_RPU_0_IDR_PMU_2_SHIFT   18
#define IPI_RPU_0_IDR_PMU_2_WIDTH   1
#define IPI_RPU_0_IDR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_RPU_0_IDR_PMU_1_SHIFT   17
#define IPI_RPU_0_IDR_PMU_1_WIDTH   1
#define IPI_RPU_0_IDR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_RPU_0_IDR_PMU_0_SHIFT   16
#define IPI_RPU_0_IDR_PMU_0_WIDTH   1
#define IPI_RPU_0_IDR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_RPU_0_IDR_RPU_1_SHIFT   9
#define IPI_RPU_0_IDR_RPU_1_WIDTH   1
#define IPI_RPU_0_IDR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_RPU_0_IDR_RPU_0_SHIFT   8
#define IPI_RPU_0_IDR_RPU_0_WIDTH   1
#define IPI_RPU_0_IDR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_RPU_0_IDR_APU_SHIFT   0
#define IPI_RPU_0_IDR_APU_WIDTH   1
#define IPI_RPU_0_IDR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_RPU_1_TRIG
 */
#define IPI_RPU_1_TRIG    ( ( IPI_BASEADDR ) + ((u32)0X00020000U) )

#define IPI_RPU_1_TRIG_PL_3_SHIFT   27
#define IPI_RPU_1_TRIG_PL_3_WIDTH   1
#define IPI_RPU_1_TRIG_PL_3_MASK    ((u32)0X08000000U)

#define IPI_RPU_1_TRIG_PL_2_SHIFT   26
#define IPI_RPU_1_TRIG_PL_2_WIDTH   1
#define IPI_RPU_1_TRIG_PL_2_MASK    ((u32)0X04000000U)

#define IPI_RPU_1_TRIG_PL_1_SHIFT   25
#define IPI_RPU_1_TRIG_PL_1_WIDTH   1
#define IPI_RPU_1_TRIG_PL_1_MASK    ((u32)0X02000000U)

#define IPI_RPU_1_TRIG_PL_0_SHIFT   24
#define IPI_RPU_1_TRIG_PL_0_WIDTH   1
#define IPI_RPU_1_TRIG_PL_0_MASK    ((u32)0X01000000U)

#define IPI_RPU_1_TRIG_PMU_3_SHIFT   19
#define IPI_RPU_1_TRIG_PMU_3_WIDTH   1
#define IPI_RPU_1_TRIG_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_RPU_1_TRIG_PMU_2_SHIFT   18
#define IPI_RPU_1_TRIG_PMU_2_WIDTH   1
#define IPI_RPU_1_TRIG_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_RPU_1_TRIG_PMU_1_SHIFT   17
#define IPI_RPU_1_TRIG_PMU_1_WIDTH   1
#define IPI_RPU_1_TRIG_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_RPU_1_TRIG_PMU_0_SHIFT   16
#define IPI_RPU_1_TRIG_PMU_0_WIDTH   1
#define IPI_RPU_1_TRIG_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_RPU_1_TRIG_RPU_1_SHIFT   9
#define IPI_RPU_1_TRIG_RPU_1_WIDTH   1
#define IPI_RPU_1_TRIG_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_RPU_1_TRIG_RPU_0_SHIFT   8
#define IPI_RPU_1_TRIG_RPU_0_WIDTH   1
#define IPI_RPU_1_TRIG_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_RPU_1_TRIG_APU_SHIFT   0
#define IPI_RPU_1_TRIG_APU_WIDTH   1
#define IPI_RPU_1_TRIG_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_RPU_1_OBS
 */
#define IPI_RPU_1_OBS    ( ( IPI_BASEADDR ) + ((u32)0X00020004U) )

#define IPI_RPU_1_OBS_PL_3_SHIFT   27
#define IPI_RPU_1_OBS_PL_3_WIDTH   1
#define IPI_RPU_1_OBS_PL_3_MASK    ((u32)0X08000000U)

#define IPI_RPU_1_OBS_PL_2_SHIFT   26
#define IPI_RPU_1_OBS_PL_2_WIDTH   1
#define IPI_RPU_1_OBS_PL_2_MASK    ((u32)0X04000000U)

#define IPI_RPU_1_OBS_PL_1_SHIFT   25
#define IPI_RPU_1_OBS_PL_1_WIDTH   1
#define IPI_RPU_1_OBS_PL_1_MASK    ((u32)0X02000000U)

#define IPI_RPU_1_OBS_PL_0_SHIFT   24
#define IPI_RPU_1_OBS_PL_0_WIDTH   1
#define IPI_RPU_1_OBS_PL_0_MASK    ((u32)0X01000000U)

#define IPI_RPU_1_OBS_PMU_3_SHIFT   19
#define IPI_RPU_1_OBS_PMU_3_WIDTH   1
#define IPI_RPU_1_OBS_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_RPU_1_OBS_PMU_2_SHIFT   18
#define IPI_RPU_1_OBS_PMU_2_WIDTH   1
#define IPI_RPU_1_OBS_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_RPU_1_OBS_PMU_1_SHIFT   17
#define IPI_RPU_1_OBS_PMU_1_WIDTH   1
#define IPI_RPU_1_OBS_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_RPU_1_OBS_PMU_0_SHIFT   16
#define IPI_RPU_1_OBS_PMU_0_WIDTH   1
#define IPI_RPU_1_OBS_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_RPU_1_OBS_RPU_1_SHIFT   9
#define IPI_RPU_1_OBS_RPU_1_WIDTH   1
#define IPI_RPU_1_OBS_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_RPU_1_OBS_RPU_0_SHIFT   8
#define IPI_RPU_1_OBS_RPU_0_WIDTH   1
#define IPI_RPU_1_OBS_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_RPU_1_OBS_APU_SHIFT   0
#define IPI_RPU_1_OBS_APU_WIDTH   1
#define IPI_RPU_1_OBS_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_RPU_1_ISR
 */
#define IPI_RPU_1_ISR    ( ( IPI_BASEADDR ) + ((u32)0X00020010U) )

#define IPI_RPU_1_ISR_PL_3_SHIFT   27
#define IPI_RPU_1_ISR_PL_3_WIDTH   1
#define IPI_RPU_1_ISR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_RPU_1_ISR_PL_2_SHIFT   26
#define IPI_RPU_1_ISR_PL_2_WIDTH   1
#define IPI_RPU_1_ISR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_RPU_1_ISR_PL_1_SHIFT   25
#define IPI_RPU_1_ISR_PL_1_WIDTH   1
#define IPI_RPU_1_ISR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_RPU_1_ISR_PL_0_SHIFT   24
#define IPI_RPU_1_ISR_PL_0_WIDTH   1
#define IPI_RPU_1_ISR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_RPU_1_ISR_PMU_3_SHIFT   19
#define IPI_RPU_1_ISR_PMU_3_WIDTH   1
#define IPI_RPU_1_ISR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_RPU_1_ISR_PMU_2_SHIFT   18
#define IPI_RPU_1_ISR_PMU_2_WIDTH   1
#define IPI_RPU_1_ISR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_RPU_1_ISR_PMU_1_SHIFT   17
#define IPI_RPU_1_ISR_PMU_1_WIDTH   1
#define IPI_RPU_1_ISR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_RPU_1_ISR_PMU_0_SHIFT   16
#define IPI_RPU_1_ISR_PMU_0_WIDTH   1
#define IPI_RPU_1_ISR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_RPU_1_ISR_RPU_1_SHIFT   9
#define IPI_RPU_1_ISR_RPU_1_WIDTH   1
#define IPI_RPU_1_ISR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_RPU_1_ISR_RPU_0_SHIFT   8
#define IPI_RPU_1_ISR_RPU_0_WIDTH   1
#define IPI_RPU_1_ISR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_RPU_1_ISR_APU_SHIFT   0
#define IPI_RPU_1_ISR_APU_WIDTH   1
#define IPI_RPU_1_ISR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_RPU_1_IMR
 */
#define IPI_RPU_1_IMR    ( ( IPI_BASEADDR ) + ((u32)0X00020014U) )

#define IPI_RPU_1_IMR_PL_3_SHIFT   27
#define IPI_RPU_1_IMR_PL_3_WIDTH   1
#define IPI_RPU_1_IMR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_RPU_1_IMR_PL_2_SHIFT   26
#define IPI_RPU_1_IMR_PL_2_WIDTH   1
#define IPI_RPU_1_IMR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_RPU_1_IMR_PL_1_SHIFT   25
#define IPI_RPU_1_IMR_PL_1_WIDTH   1
#define IPI_RPU_1_IMR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_RPU_1_IMR_PL_0_SHIFT   24
#define IPI_RPU_1_IMR_PL_0_WIDTH   1
#define IPI_RPU_1_IMR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_RPU_1_IMR_PMU_3_SHIFT   19
#define IPI_RPU_1_IMR_PMU_3_WIDTH   1
#define IPI_RPU_1_IMR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_RPU_1_IMR_PMU_2_SHIFT   18
#define IPI_RPU_1_IMR_PMU_2_WIDTH   1
#define IPI_RPU_1_IMR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_RPU_1_IMR_PMU_1_SHIFT   17
#define IPI_RPU_1_IMR_PMU_1_WIDTH   1
#define IPI_RPU_1_IMR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_RPU_1_IMR_PMU_0_SHIFT   16
#define IPI_RPU_1_IMR_PMU_0_WIDTH   1
#define IPI_RPU_1_IMR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_RPU_1_IMR_RPU_1_SHIFT   9
#define IPI_RPU_1_IMR_RPU_1_WIDTH   1
#define IPI_RPU_1_IMR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_RPU_1_IMR_RPU_0_SHIFT   8
#define IPI_RPU_1_IMR_RPU_0_WIDTH   1
#define IPI_RPU_1_IMR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_RPU_1_IMR_APU_SHIFT   0
#define IPI_RPU_1_IMR_APU_WIDTH   1
#define IPI_RPU_1_IMR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_RPU_1_IER
 */
#define IPI_RPU_1_IER    ( ( IPI_BASEADDR ) + ((u32)0X00020018U) )

#define IPI_RPU_1_IER_PL_3_SHIFT   27
#define IPI_RPU_1_IER_PL_3_WIDTH   1
#define IPI_RPU_1_IER_PL_3_MASK    ((u32)0X08000000U)

#define IPI_RPU_1_IER_PL_2_SHIFT   26
#define IPI_RPU_1_IER_PL_2_WIDTH   1
#define IPI_RPU_1_IER_PL_2_MASK    ((u32)0X04000000U)

#define IPI_RPU_1_IER_PL_1_SHIFT   25
#define IPI_RPU_1_IER_PL_1_WIDTH   1
#define IPI_RPU_1_IER_PL_1_MASK    ((u32)0X02000000U)

#define IPI_RPU_1_IER_PL_0_SHIFT   24
#define IPI_RPU_1_IER_PL_0_WIDTH   1
#define IPI_RPU_1_IER_PL_0_MASK    ((u32)0X01000000U)

#define IPI_RPU_1_IER_PMU_3_SHIFT   19
#define IPI_RPU_1_IER_PMU_3_WIDTH   1
#define IPI_RPU_1_IER_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_RPU_1_IER_PMU_2_SHIFT   18
#define IPI_RPU_1_IER_PMU_2_WIDTH   1
#define IPI_RPU_1_IER_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_RPU_1_IER_PMU_1_SHIFT   17
#define IPI_RPU_1_IER_PMU_1_WIDTH   1
#define IPI_RPU_1_IER_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_RPU_1_IER_PMU_0_SHIFT   16
#define IPI_RPU_1_IER_PMU_0_WIDTH   1
#define IPI_RPU_1_IER_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_RPU_1_IER_RPU_1_SHIFT   9
#define IPI_RPU_1_IER_RPU_1_WIDTH   1
#define IPI_RPU_1_IER_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_RPU_1_IER_RPU_0_SHIFT   8
#define IPI_RPU_1_IER_RPU_0_WIDTH   1
#define IPI_RPU_1_IER_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_RPU_1_IER_APU_SHIFT   0
#define IPI_RPU_1_IER_APU_WIDTH   1
#define IPI_RPU_1_IER_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_RPU_1_IDR
 */
#define IPI_RPU_1_IDR    ( ( IPI_BASEADDR ) + ((u32)0X0002001CU) )

#define IPI_RPU_1_IDR_PL_3_SHIFT   27
#define IPI_RPU_1_IDR_PL_3_WIDTH   1
#define IPI_RPU_1_IDR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_RPU_1_IDR_PL_2_SHIFT   26
#define IPI_RPU_1_IDR_PL_2_WIDTH   1
#define IPI_RPU_1_IDR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_RPU_1_IDR_PL_1_SHIFT   25
#define IPI_RPU_1_IDR_PL_1_WIDTH   1
#define IPI_RPU_1_IDR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_RPU_1_IDR_PL_0_SHIFT   24
#define IPI_RPU_1_IDR_PL_0_WIDTH   1
#define IPI_RPU_1_IDR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_RPU_1_IDR_PMU_3_SHIFT   19
#define IPI_RPU_1_IDR_PMU_3_WIDTH   1
#define IPI_RPU_1_IDR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_RPU_1_IDR_PMU_2_SHIFT   18
#define IPI_RPU_1_IDR_PMU_2_WIDTH   1
#define IPI_RPU_1_IDR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_RPU_1_IDR_PMU_1_SHIFT   17
#define IPI_RPU_1_IDR_PMU_1_WIDTH   1
#define IPI_RPU_1_IDR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_RPU_1_IDR_PMU_0_SHIFT   16
#define IPI_RPU_1_IDR_PMU_0_WIDTH   1
#define IPI_RPU_1_IDR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_RPU_1_IDR_RPU_1_SHIFT   9
#define IPI_RPU_1_IDR_RPU_1_WIDTH   1
#define IPI_RPU_1_IDR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_RPU_1_IDR_RPU_0_SHIFT   8
#define IPI_RPU_1_IDR_RPU_0_WIDTH   1
#define IPI_RPU_1_IDR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_RPU_1_IDR_APU_SHIFT   0
#define IPI_RPU_1_IDR_APU_WIDTH   1
#define IPI_RPU_1_IDR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_0_TRIG
 */
#define IPI_PMU_0_TRIG    ( ( IPI_BASEADDR ) + ((u32)0X00030000U) )

#define IPI_PMU_0_TRIG_PL_3_SHIFT   27
#define IPI_PMU_0_TRIG_PL_3_WIDTH   1
#define IPI_PMU_0_TRIG_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_0_TRIG_PL_2_SHIFT   26
#define IPI_PMU_0_TRIG_PL_2_WIDTH   1
#define IPI_PMU_0_TRIG_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_0_TRIG_PL_1_SHIFT   25
#define IPI_PMU_0_TRIG_PL_1_WIDTH   1
#define IPI_PMU_0_TRIG_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_0_TRIG_PL_0_SHIFT   24
#define IPI_PMU_0_TRIG_PL_0_WIDTH   1
#define IPI_PMU_0_TRIG_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_0_TRIG_PMU_3_SHIFT   19
#define IPI_PMU_0_TRIG_PMU_3_WIDTH   1
#define IPI_PMU_0_TRIG_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_0_TRIG_PMU_2_SHIFT   18
#define IPI_PMU_0_TRIG_PMU_2_WIDTH   1
#define IPI_PMU_0_TRIG_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_0_TRIG_PMU_1_SHIFT   17
#define IPI_PMU_0_TRIG_PMU_1_WIDTH   1
#define IPI_PMU_0_TRIG_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_0_TRIG_PMU_0_SHIFT   16
#define IPI_PMU_0_TRIG_PMU_0_WIDTH   1
#define IPI_PMU_0_TRIG_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_0_TRIG_RPU_1_SHIFT   9
#define IPI_PMU_0_TRIG_RPU_1_WIDTH   1
#define IPI_PMU_0_TRIG_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_0_TRIG_RPU_0_SHIFT   8
#define IPI_PMU_0_TRIG_RPU_0_WIDTH   1
#define IPI_PMU_0_TRIG_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_0_TRIG_APU_SHIFT   0
#define IPI_PMU_0_TRIG_APU_WIDTH   1
#define IPI_PMU_0_TRIG_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_0_OBS
 */
#define IPI_PMU_0_OBS    ( ( IPI_BASEADDR ) + ((u32)0X00030004U) )

#define IPI_PMU_0_OBS_PL_3_SHIFT   27
#define IPI_PMU_0_OBS_PL_3_WIDTH   1
#define IPI_PMU_0_OBS_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_0_OBS_PL_2_SHIFT   26
#define IPI_PMU_0_OBS_PL_2_WIDTH   1
#define IPI_PMU_0_OBS_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_0_OBS_PL_1_SHIFT   25
#define IPI_PMU_0_OBS_PL_1_WIDTH   1
#define IPI_PMU_0_OBS_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_0_OBS_PL_0_SHIFT   24
#define IPI_PMU_0_OBS_PL_0_WIDTH   1
#define IPI_PMU_0_OBS_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_0_OBS_PMU_3_SHIFT   19
#define IPI_PMU_0_OBS_PMU_3_WIDTH   1
#define IPI_PMU_0_OBS_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_0_OBS_PMU_2_SHIFT   18
#define IPI_PMU_0_OBS_PMU_2_WIDTH   1
#define IPI_PMU_0_OBS_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_0_OBS_PMU_1_SHIFT   17
#define IPI_PMU_0_OBS_PMU_1_WIDTH   1
#define IPI_PMU_0_OBS_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_0_OBS_PMU_0_SHIFT   16
#define IPI_PMU_0_OBS_PMU_0_WIDTH   1
#define IPI_PMU_0_OBS_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_0_OBS_RPU_1_SHIFT   9
#define IPI_PMU_0_OBS_RPU_1_WIDTH   1
#define IPI_PMU_0_OBS_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_0_OBS_RPU_0_SHIFT   8
#define IPI_PMU_0_OBS_RPU_0_WIDTH   1
#define IPI_PMU_0_OBS_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_0_OBS_APU_SHIFT   0
#define IPI_PMU_0_OBS_APU_WIDTH   1
#define IPI_PMU_0_OBS_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_0_ISR
 */
#define IPI_PMU_0_ISR    ( ( IPI_BASEADDR ) + ((u32)0X00030010U) )

#define IPI_PMU_0_ISR_PL_3_SHIFT   27
#define IPI_PMU_0_ISR_PL_3_WIDTH   1
#define IPI_PMU_0_ISR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_0_ISR_PL_2_SHIFT   26
#define IPI_PMU_0_ISR_PL_2_WIDTH   1
#define IPI_PMU_0_ISR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_0_ISR_PL_1_SHIFT   25
#define IPI_PMU_0_ISR_PL_1_WIDTH   1
#define IPI_PMU_0_ISR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_0_ISR_PL_0_SHIFT   24
#define IPI_PMU_0_ISR_PL_0_WIDTH   1
#define IPI_PMU_0_ISR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_0_ISR_PMU_3_SHIFT   19
#define IPI_PMU_0_ISR_PMU_3_WIDTH   1
#define IPI_PMU_0_ISR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_0_ISR_PMU_2_SHIFT   18
#define IPI_PMU_0_ISR_PMU_2_WIDTH   1
#define IPI_PMU_0_ISR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_0_ISR_PMU_1_SHIFT   17
#define IPI_PMU_0_ISR_PMU_1_WIDTH   1
#define IPI_PMU_0_ISR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_0_ISR_PMU_0_SHIFT   16
#define IPI_PMU_0_ISR_PMU_0_WIDTH   1
#define IPI_PMU_0_ISR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_0_ISR_RPU_1_SHIFT   9
#define IPI_PMU_0_ISR_RPU_1_WIDTH   1
#define IPI_PMU_0_ISR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_0_ISR_RPU_0_SHIFT   8
#define IPI_PMU_0_ISR_RPU_0_WIDTH   1
#define IPI_PMU_0_ISR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_0_ISR_APU_SHIFT   0
#define IPI_PMU_0_ISR_APU_WIDTH   1
#define IPI_PMU_0_ISR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_0_IMR
 */
#define IPI_PMU_0_IMR    ( ( IPI_BASEADDR ) + ((u32)0X00030014U) )

#define IPI_PMU_0_IMR_PL_3_SHIFT   27
#define IPI_PMU_0_IMR_PL_3_WIDTH   1
#define IPI_PMU_0_IMR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_0_IMR_PL_2_SHIFT   26
#define IPI_PMU_0_IMR_PL_2_WIDTH   1
#define IPI_PMU_0_IMR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_0_IMR_PL_1_SHIFT   25
#define IPI_PMU_0_IMR_PL_1_WIDTH   1
#define IPI_PMU_0_IMR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_0_IMR_PL_0_SHIFT   24
#define IPI_PMU_0_IMR_PL_0_WIDTH   1
#define IPI_PMU_0_IMR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_0_IMR_PMU_3_SHIFT   19
#define IPI_PMU_0_IMR_PMU_3_WIDTH   1
#define IPI_PMU_0_IMR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_0_IMR_PMU_2_SHIFT   18
#define IPI_PMU_0_IMR_PMU_2_WIDTH   1
#define IPI_PMU_0_IMR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_0_IMR_PMU_1_SHIFT   17
#define IPI_PMU_0_IMR_PMU_1_WIDTH   1
#define IPI_PMU_0_IMR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_0_IMR_PMU_0_SHIFT   16
#define IPI_PMU_0_IMR_PMU_0_WIDTH   1
#define IPI_PMU_0_IMR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_0_IMR_RPU_1_SHIFT   9
#define IPI_PMU_0_IMR_RPU_1_WIDTH   1
#define IPI_PMU_0_IMR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_0_IMR_RPU_0_SHIFT   8
#define IPI_PMU_0_IMR_RPU_0_WIDTH   1
#define IPI_PMU_0_IMR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_0_IMR_APU_SHIFT   0
#define IPI_PMU_0_IMR_APU_WIDTH   1
#define IPI_PMU_0_IMR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_0_IER
 */
#define IPI_PMU_0_IER    ( ( IPI_BASEADDR ) + ((u32)0X00030018U) )

#define IPI_PMU_0_IER_PL_3_SHIFT   27
#define IPI_PMU_0_IER_PL_3_WIDTH   1
#define IPI_PMU_0_IER_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_0_IER_PL_2_SHIFT   26
#define IPI_PMU_0_IER_PL_2_WIDTH   1
#define IPI_PMU_0_IER_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_0_IER_PL_1_SHIFT   25
#define IPI_PMU_0_IER_PL_1_WIDTH   1
#define IPI_PMU_0_IER_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_0_IER_PL_0_SHIFT   24
#define IPI_PMU_0_IER_PL_0_WIDTH   1
#define IPI_PMU_0_IER_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_0_IER_PMU_3_SHIFT   19
#define IPI_PMU_0_IER_PMU_3_WIDTH   1
#define IPI_PMU_0_IER_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_0_IER_PMU_2_SHIFT   18
#define IPI_PMU_0_IER_PMU_2_WIDTH   1
#define IPI_PMU_0_IER_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_0_IER_PMU_1_SHIFT   17
#define IPI_PMU_0_IER_PMU_1_WIDTH   1
#define IPI_PMU_0_IER_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_0_IER_PMU_0_SHIFT   16
#define IPI_PMU_0_IER_PMU_0_WIDTH   1
#define IPI_PMU_0_IER_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_0_IER_RPU_1_SHIFT   9
#define IPI_PMU_0_IER_RPU_1_WIDTH   1
#define IPI_PMU_0_IER_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_0_IER_RPU_0_SHIFT   8
#define IPI_PMU_0_IER_RPU_0_WIDTH   1
#define IPI_PMU_0_IER_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_0_IER_APU_SHIFT   0
#define IPI_PMU_0_IER_APU_WIDTH   1
#define IPI_PMU_0_IER_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_0_IDR
 */
#define IPI_PMU_0_IDR    ( ( IPI_BASEADDR ) + ((u32)0X0003001CU) )

#define IPI_PMU_0_IDR_PL_3_SHIFT   27
#define IPI_PMU_0_IDR_PL_3_WIDTH   1
#define IPI_PMU_0_IDR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_0_IDR_PL_2_SHIFT   26
#define IPI_PMU_0_IDR_PL_2_WIDTH   1
#define IPI_PMU_0_IDR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_0_IDR_PL_1_SHIFT   25
#define IPI_PMU_0_IDR_PL_1_WIDTH   1
#define IPI_PMU_0_IDR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_0_IDR_PL_0_SHIFT   24
#define IPI_PMU_0_IDR_PL_0_WIDTH   1
#define IPI_PMU_0_IDR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_0_IDR_PMU_3_SHIFT   19
#define IPI_PMU_0_IDR_PMU_3_WIDTH   1
#define IPI_PMU_0_IDR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_0_IDR_PMU_2_SHIFT   18
#define IPI_PMU_0_IDR_PMU_2_WIDTH   1
#define IPI_PMU_0_IDR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_0_IDR_PMU_1_SHIFT   17
#define IPI_PMU_0_IDR_PMU_1_WIDTH   1
#define IPI_PMU_0_IDR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_0_IDR_PMU_0_SHIFT   16
#define IPI_PMU_0_IDR_PMU_0_WIDTH   1
#define IPI_PMU_0_IDR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_0_IDR_RPU_1_SHIFT   9
#define IPI_PMU_0_IDR_RPU_1_WIDTH   1
#define IPI_PMU_0_IDR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_0_IDR_RPU_0_SHIFT   8
#define IPI_PMU_0_IDR_RPU_0_WIDTH   1
#define IPI_PMU_0_IDR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_0_IDR_APU_SHIFT   0
#define IPI_PMU_0_IDR_APU_WIDTH   1
#define IPI_PMU_0_IDR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_1_TRIG
 */
#define IPI_PMU_1_TRIG    ( ( IPI_BASEADDR ) + ((u32)0X00031000U) )

#define IPI_PMU_1_TRIG_PL_3_SHIFT   27
#define IPI_PMU_1_TRIG_PL_3_WIDTH   1
#define IPI_PMU_1_TRIG_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_1_TRIG_PL_2_SHIFT   26
#define IPI_PMU_1_TRIG_PL_2_WIDTH   1
#define IPI_PMU_1_TRIG_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_1_TRIG_PL_1_SHIFT   25
#define IPI_PMU_1_TRIG_PL_1_WIDTH   1
#define IPI_PMU_1_TRIG_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_1_TRIG_PL_0_SHIFT   24
#define IPI_PMU_1_TRIG_PL_0_WIDTH   1
#define IPI_PMU_1_TRIG_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_1_TRIG_PMU_3_SHIFT   19
#define IPI_PMU_1_TRIG_PMU_3_WIDTH   1
#define IPI_PMU_1_TRIG_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_1_TRIG_PMU_2_SHIFT   18
#define IPI_PMU_1_TRIG_PMU_2_WIDTH   1
#define IPI_PMU_1_TRIG_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_1_TRIG_PMU_1_SHIFT   17
#define IPI_PMU_1_TRIG_PMU_1_WIDTH   1
#define IPI_PMU_1_TRIG_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_1_TRIG_PMU_0_SHIFT   16
#define IPI_PMU_1_TRIG_PMU_0_WIDTH   1
#define IPI_PMU_1_TRIG_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_1_TRIG_RPU_1_SHIFT   9
#define IPI_PMU_1_TRIG_RPU_1_WIDTH   1
#define IPI_PMU_1_TRIG_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_1_TRIG_RPU_0_SHIFT   8
#define IPI_PMU_1_TRIG_RPU_0_WIDTH   1
#define IPI_PMU_1_TRIG_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_1_TRIG_APU_SHIFT   0
#define IPI_PMU_1_TRIG_APU_WIDTH   1
#define IPI_PMU_1_TRIG_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_1_OBS
 */
#define IPI_PMU_1_OBS    ( ( IPI_BASEADDR ) + ((u32)0X00031004U) )

#define IPI_PMU_1_OBS_PL_3_SHIFT   27
#define IPI_PMU_1_OBS_PL_3_WIDTH   1
#define IPI_PMU_1_OBS_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_1_OBS_PL_2_SHIFT   26
#define IPI_PMU_1_OBS_PL_2_WIDTH   1
#define IPI_PMU_1_OBS_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_1_OBS_PL_1_SHIFT   25
#define IPI_PMU_1_OBS_PL_1_WIDTH   1
#define IPI_PMU_1_OBS_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_1_OBS_PL_0_SHIFT   24
#define IPI_PMU_1_OBS_PL_0_WIDTH   1
#define IPI_PMU_1_OBS_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_1_OBS_PMU_3_SHIFT   19
#define IPI_PMU_1_OBS_PMU_3_WIDTH   1
#define IPI_PMU_1_OBS_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_1_OBS_PMU_2_SHIFT   18
#define IPI_PMU_1_OBS_PMU_2_WIDTH   1
#define IPI_PMU_1_OBS_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_1_OBS_PMU_1_SHIFT   17
#define IPI_PMU_1_OBS_PMU_1_WIDTH   1
#define IPI_PMU_1_OBS_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_1_OBS_PMU_0_SHIFT   16
#define IPI_PMU_1_OBS_PMU_0_WIDTH   1
#define IPI_PMU_1_OBS_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_1_OBS_RPU_1_SHIFT   9
#define IPI_PMU_1_OBS_RPU_1_WIDTH   1
#define IPI_PMU_1_OBS_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_1_OBS_RPU_0_SHIFT   8
#define IPI_PMU_1_OBS_RPU_0_WIDTH   1
#define IPI_PMU_1_OBS_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_1_OBS_APU_SHIFT   0
#define IPI_PMU_1_OBS_APU_WIDTH   1
#define IPI_PMU_1_OBS_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_1_ISR
 */
#define IPI_PMU_1_ISR    ( ( IPI_BASEADDR ) + ((u32)0X00031010U) )

#define IPI_PMU_1_ISR_PL_3_SHIFT   27
#define IPI_PMU_1_ISR_PL_3_WIDTH   1
#define IPI_PMU_1_ISR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_1_ISR_PL_2_SHIFT   26
#define IPI_PMU_1_ISR_PL_2_WIDTH   1
#define IPI_PMU_1_ISR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_1_ISR_PL_1_SHIFT   25
#define IPI_PMU_1_ISR_PL_1_WIDTH   1
#define IPI_PMU_1_ISR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_1_ISR_PL_0_SHIFT   24
#define IPI_PMU_1_ISR_PL_0_WIDTH   1
#define IPI_PMU_1_ISR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_1_ISR_PMU_3_SHIFT   19
#define IPI_PMU_1_ISR_PMU_3_WIDTH   1
#define IPI_PMU_1_ISR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_1_ISR_PMU_2_SHIFT   18
#define IPI_PMU_1_ISR_PMU_2_WIDTH   1
#define IPI_PMU_1_ISR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_1_ISR_PMU_1_SHIFT   17
#define IPI_PMU_1_ISR_PMU_1_WIDTH   1
#define IPI_PMU_1_ISR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_1_ISR_PMU_0_SHIFT   16
#define IPI_PMU_1_ISR_PMU_0_WIDTH   1
#define IPI_PMU_1_ISR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_1_ISR_RPU_1_SHIFT   9
#define IPI_PMU_1_ISR_RPU_1_WIDTH   1
#define IPI_PMU_1_ISR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_1_ISR_RPU_0_SHIFT   8
#define IPI_PMU_1_ISR_RPU_0_WIDTH   1
#define IPI_PMU_1_ISR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_1_ISR_APU_SHIFT   0
#define IPI_PMU_1_ISR_APU_WIDTH   1
#define IPI_PMU_1_ISR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_1_IMR
 */
#define IPI_PMU_1_IMR    ( ( IPI_BASEADDR ) + ((u32)0X00031014U) )

#define IPI_PMU_1_IMR_PL_3_SHIFT   27
#define IPI_PMU_1_IMR_PL_3_WIDTH   1
#define IPI_PMU_1_IMR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_1_IMR_PL_2_SHIFT   26
#define IPI_PMU_1_IMR_PL_2_WIDTH   1
#define IPI_PMU_1_IMR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_1_IMR_PL_1_SHIFT   25
#define IPI_PMU_1_IMR_PL_1_WIDTH   1
#define IPI_PMU_1_IMR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_1_IMR_PL_0_SHIFT   24
#define IPI_PMU_1_IMR_PL_0_WIDTH   1
#define IPI_PMU_1_IMR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_1_IMR_PMU_3_SHIFT   19
#define IPI_PMU_1_IMR_PMU_3_WIDTH   1
#define IPI_PMU_1_IMR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_1_IMR_PMU_2_SHIFT   18
#define IPI_PMU_1_IMR_PMU_2_WIDTH   1
#define IPI_PMU_1_IMR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_1_IMR_PMU_1_SHIFT   17
#define IPI_PMU_1_IMR_PMU_1_WIDTH   1
#define IPI_PMU_1_IMR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_1_IMR_PMU_0_SHIFT   16
#define IPI_PMU_1_IMR_PMU_0_WIDTH   1
#define IPI_PMU_1_IMR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_1_IMR_RPU_1_SHIFT   9
#define IPI_PMU_1_IMR_RPU_1_WIDTH   1
#define IPI_PMU_1_IMR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_1_IMR_RPU_0_SHIFT   8
#define IPI_PMU_1_IMR_RPU_0_WIDTH   1
#define IPI_PMU_1_IMR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_1_IMR_APU_SHIFT   0
#define IPI_PMU_1_IMR_APU_WIDTH   1
#define IPI_PMU_1_IMR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_1_IER
 */
#define IPI_PMU_1_IER    ( ( IPI_BASEADDR ) + ((u32)0X00031018U) )

#define IPI_PMU_1_IER_PL_3_SHIFT   27
#define IPI_PMU_1_IER_PL_3_WIDTH   1
#define IPI_PMU_1_IER_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_1_IER_PL_2_SHIFT   26
#define IPI_PMU_1_IER_PL_2_WIDTH   1
#define IPI_PMU_1_IER_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_1_IER_PL_1_SHIFT   25
#define IPI_PMU_1_IER_PL_1_WIDTH   1
#define IPI_PMU_1_IER_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_1_IER_PL_0_SHIFT   24
#define IPI_PMU_1_IER_PL_0_WIDTH   1
#define IPI_PMU_1_IER_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_1_IER_PMU_3_SHIFT   19
#define IPI_PMU_1_IER_PMU_3_WIDTH   1
#define IPI_PMU_1_IER_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_1_IER_PMU_2_SHIFT   18
#define IPI_PMU_1_IER_PMU_2_WIDTH   1
#define IPI_PMU_1_IER_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_1_IER_PMU_1_SHIFT   17
#define IPI_PMU_1_IER_PMU_1_WIDTH   1
#define IPI_PMU_1_IER_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_1_IER_PMU_0_SHIFT   16
#define IPI_PMU_1_IER_PMU_0_WIDTH   1
#define IPI_PMU_1_IER_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_1_IER_RPU_1_SHIFT   9
#define IPI_PMU_1_IER_RPU_1_WIDTH   1
#define IPI_PMU_1_IER_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_1_IER_RPU_0_SHIFT   8
#define IPI_PMU_1_IER_RPU_0_WIDTH   1
#define IPI_PMU_1_IER_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_1_IER_APU_SHIFT   0
#define IPI_PMU_1_IER_APU_WIDTH   1
#define IPI_PMU_1_IER_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_1_IDR
 */
#define IPI_PMU_1_IDR    ( ( IPI_BASEADDR ) + ((u32)0X0003101CU) )

#define IPI_PMU_1_IDR_PL_3_SHIFT   27
#define IPI_PMU_1_IDR_PL_3_WIDTH   1
#define IPI_PMU_1_IDR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_1_IDR_PL_2_SHIFT   26
#define IPI_PMU_1_IDR_PL_2_WIDTH   1
#define IPI_PMU_1_IDR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_1_IDR_PL_1_SHIFT   25
#define IPI_PMU_1_IDR_PL_1_WIDTH   1
#define IPI_PMU_1_IDR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_1_IDR_PL_0_SHIFT   24
#define IPI_PMU_1_IDR_PL_0_WIDTH   1
#define IPI_PMU_1_IDR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_1_IDR_PMU_3_SHIFT   19
#define IPI_PMU_1_IDR_PMU_3_WIDTH   1
#define IPI_PMU_1_IDR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_1_IDR_PMU_2_SHIFT   18
#define IPI_PMU_1_IDR_PMU_2_WIDTH   1
#define IPI_PMU_1_IDR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_1_IDR_PMU_1_SHIFT   17
#define IPI_PMU_1_IDR_PMU_1_WIDTH   1
#define IPI_PMU_1_IDR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_1_IDR_PMU_0_SHIFT   16
#define IPI_PMU_1_IDR_PMU_0_WIDTH   1
#define IPI_PMU_1_IDR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_1_IDR_RPU_1_SHIFT   9
#define IPI_PMU_1_IDR_RPU_1_WIDTH   1
#define IPI_PMU_1_IDR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_1_IDR_RPU_0_SHIFT   8
#define IPI_PMU_1_IDR_RPU_0_WIDTH   1
#define IPI_PMU_1_IDR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_1_IDR_APU_SHIFT   0
#define IPI_PMU_1_IDR_APU_WIDTH   1
#define IPI_PMU_1_IDR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_2_TRIG
 */
#define IPI_PMU_2_TRIG    ( ( IPI_BASEADDR ) + ((u32)0X00032000U) )

#define IPI_PMU_2_TRIG_PL_3_SHIFT   27
#define IPI_PMU_2_TRIG_PL_3_WIDTH   1
#define IPI_PMU_2_TRIG_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_2_TRIG_PL_2_SHIFT   26
#define IPI_PMU_2_TRIG_PL_2_WIDTH   1
#define IPI_PMU_2_TRIG_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_2_TRIG_PL_1_SHIFT   25
#define IPI_PMU_2_TRIG_PL_1_WIDTH   1
#define IPI_PMU_2_TRIG_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_2_TRIG_PL_0_SHIFT   24
#define IPI_PMU_2_TRIG_PL_0_WIDTH   1
#define IPI_PMU_2_TRIG_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_2_TRIG_PMU_3_SHIFT   19
#define IPI_PMU_2_TRIG_PMU_3_WIDTH   1
#define IPI_PMU_2_TRIG_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_2_TRIG_PMU_2_SHIFT   18
#define IPI_PMU_2_TRIG_PMU_2_WIDTH   1
#define IPI_PMU_2_TRIG_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_2_TRIG_PMU_1_SHIFT   17
#define IPI_PMU_2_TRIG_PMU_1_WIDTH   1
#define IPI_PMU_2_TRIG_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_2_TRIG_PMU_0_SHIFT   16
#define IPI_PMU_2_TRIG_PMU_0_WIDTH   1
#define IPI_PMU_2_TRIG_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_2_TRIG_RPU_1_SHIFT   9
#define IPI_PMU_2_TRIG_RPU_1_WIDTH   1
#define IPI_PMU_2_TRIG_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_2_TRIG_RPU_0_SHIFT   8
#define IPI_PMU_2_TRIG_RPU_0_WIDTH   1
#define IPI_PMU_2_TRIG_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_2_TRIG_APU_SHIFT   0
#define IPI_PMU_2_TRIG_APU_WIDTH   1
#define IPI_PMU_2_TRIG_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_2_OBS
 */
#define IPI_PMU_2_OBS    ( ( IPI_BASEADDR ) + ((u32)0X00032004U) )

#define IPI_PMU_2_OBS_PL_3_SHIFT   27
#define IPI_PMU_2_OBS_PL_3_WIDTH   1
#define IPI_PMU_2_OBS_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_2_OBS_PL_2_SHIFT   26
#define IPI_PMU_2_OBS_PL_2_WIDTH   1
#define IPI_PMU_2_OBS_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_2_OBS_PL_1_SHIFT   25
#define IPI_PMU_2_OBS_PL_1_WIDTH   1
#define IPI_PMU_2_OBS_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_2_OBS_PL_0_SHIFT   24
#define IPI_PMU_2_OBS_PL_0_WIDTH   1
#define IPI_PMU_2_OBS_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_2_OBS_PMU_3_SHIFT   19
#define IPI_PMU_2_OBS_PMU_3_WIDTH   1
#define IPI_PMU_2_OBS_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_2_OBS_PMU_2_SHIFT   18
#define IPI_PMU_2_OBS_PMU_2_WIDTH   1
#define IPI_PMU_2_OBS_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_2_OBS_PMU_1_SHIFT   17
#define IPI_PMU_2_OBS_PMU_1_WIDTH   1
#define IPI_PMU_2_OBS_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_2_OBS_PMU_0_SHIFT   16
#define IPI_PMU_2_OBS_PMU_0_WIDTH   1
#define IPI_PMU_2_OBS_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_2_OBS_RPU_1_SHIFT   9
#define IPI_PMU_2_OBS_RPU_1_WIDTH   1
#define IPI_PMU_2_OBS_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_2_OBS_RPU_0_SHIFT   8
#define IPI_PMU_2_OBS_RPU_0_WIDTH   1
#define IPI_PMU_2_OBS_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_2_OBS_APU_SHIFT   0
#define IPI_PMU_2_OBS_APU_WIDTH   1
#define IPI_PMU_2_OBS_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_2_ISR
 */
#define IPI_PMU_2_ISR    ( ( IPI_BASEADDR ) + ((u32)0X00032010U) )

#define IPI_PMU_2_ISR_PL_3_SHIFT   27
#define IPI_PMU_2_ISR_PL_3_WIDTH   1
#define IPI_PMU_2_ISR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_2_ISR_PL_2_SHIFT   26
#define IPI_PMU_2_ISR_PL_2_WIDTH   1
#define IPI_PMU_2_ISR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_2_ISR_PL_1_SHIFT   25
#define IPI_PMU_2_ISR_PL_1_WIDTH   1
#define IPI_PMU_2_ISR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_2_ISR_PL_0_SHIFT   24
#define IPI_PMU_2_ISR_PL_0_WIDTH   1
#define IPI_PMU_2_ISR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_2_ISR_PMU_3_SHIFT   19
#define IPI_PMU_2_ISR_PMU_3_WIDTH   1
#define IPI_PMU_2_ISR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_2_ISR_PMU_2_SHIFT   18
#define IPI_PMU_2_ISR_PMU_2_WIDTH   1
#define IPI_PMU_2_ISR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_2_ISR_PMU_1_SHIFT   17
#define IPI_PMU_2_ISR_PMU_1_WIDTH   1
#define IPI_PMU_2_ISR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_2_ISR_PMU_0_SHIFT   16
#define IPI_PMU_2_ISR_PMU_0_WIDTH   1
#define IPI_PMU_2_ISR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_2_ISR_RPU_1_SHIFT   9
#define IPI_PMU_2_ISR_RPU_1_WIDTH   1
#define IPI_PMU_2_ISR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_2_ISR_RPU_0_SHIFT   8
#define IPI_PMU_2_ISR_RPU_0_WIDTH   1
#define IPI_PMU_2_ISR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_2_ISR_APU_SHIFT   0
#define IPI_PMU_2_ISR_APU_WIDTH   1
#define IPI_PMU_2_ISR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_2_IMR
 */
#define IPI_PMU_2_IMR    ( ( IPI_BASEADDR ) + ((u32)0X00032014U) )

#define IPI_PMU_2_IMR_PL_3_SHIFT   27
#define IPI_PMU_2_IMR_PL_3_WIDTH   1
#define IPI_PMU_2_IMR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_2_IMR_PL_2_SHIFT   26
#define IPI_PMU_2_IMR_PL_2_WIDTH   1
#define IPI_PMU_2_IMR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_2_IMR_PL_1_SHIFT   25
#define IPI_PMU_2_IMR_PL_1_WIDTH   1
#define IPI_PMU_2_IMR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_2_IMR_PL_0_SHIFT   24
#define IPI_PMU_2_IMR_PL_0_WIDTH   1
#define IPI_PMU_2_IMR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_2_IMR_PMU_3_SHIFT   19
#define IPI_PMU_2_IMR_PMU_3_WIDTH   1
#define IPI_PMU_2_IMR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_2_IMR_PMU_2_SHIFT   18
#define IPI_PMU_2_IMR_PMU_2_WIDTH   1
#define IPI_PMU_2_IMR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_2_IMR_PMU_1_SHIFT   17
#define IPI_PMU_2_IMR_PMU_1_WIDTH   1
#define IPI_PMU_2_IMR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_2_IMR_PMU_0_SHIFT   16
#define IPI_PMU_2_IMR_PMU_0_WIDTH   1
#define IPI_PMU_2_IMR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_2_IMR_RPU_1_SHIFT   9
#define IPI_PMU_2_IMR_RPU_1_WIDTH   1
#define IPI_PMU_2_IMR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_2_IMR_RPU_0_SHIFT   8
#define IPI_PMU_2_IMR_RPU_0_WIDTH   1
#define IPI_PMU_2_IMR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_2_IMR_APU_SHIFT   0
#define IPI_PMU_2_IMR_APU_WIDTH   1
#define IPI_PMU_2_IMR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_2_IER
 */
#define IPI_PMU_2_IER    ( ( IPI_BASEADDR ) + ((u32)0X00032018U) )

#define IPI_PMU_2_IER_PL_3_SHIFT   27
#define IPI_PMU_2_IER_PL_3_WIDTH   1
#define IPI_PMU_2_IER_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_2_IER_PL_2_SHIFT   26
#define IPI_PMU_2_IER_PL_2_WIDTH   1
#define IPI_PMU_2_IER_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_2_IER_PL_1_SHIFT   25
#define IPI_PMU_2_IER_PL_1_WIDTH   1
#define IPI_PMU_2_IER_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_2_IER_PL_0_SHIFT   24
#define IPI_PMU_2_IER_PL_0_WIDTH   1
#define IPI_PMU_2_IER_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_2_IER_PMU_3_SHIFT   19
#define IPI_PMU_2_IER_PMU_3_WIDTH   1
#define IPI_PMU_2_IER_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_2_IER_PMU_2_SHIFT   18
#define IPI_PMU_2_IER_PMU_2_WIDTH   1
#define IPI_PMU_2_IER_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_2_IER_PMU_1_SHIFT   17
#define IPI_PMU_2_IER_PMU_1_WIDTH   1
#define IPI_PMU_2_IER_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_2_IER_PMU_0_SHIFT   16
#define IPI_PMU_2_IER_PMU_0_WIDTH   1
#define IPI_PMU_2_IER_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_2_IER_RPU_1_SHIFT   9
#define IPI_PMU_2_IER_RPU_1_WIDTH   1
#define IPI_PMU_2_IER_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_2_IER_RPU_0_SHIFT   8
#define IPI_PMU_2_IER_RPU_0_WIDTH   1
#define IPI_PMU_2_IER_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_2_IER_APU_SHIFT   0
#define IPI_PMU_2_IER_APU_WIDTH   1
#define IPI_PMU_2_IER_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_2_IDR
 */
#define IPI_PMU_2_IDR    ( ( IPI_BASEADDR ) + ((u32)0X0003201CU) )

#define IPI_PMU_2_IDR_PL_3_SHIFT   27
#define IPI_PMU_2_IDR_PL_3_WIDTH   1
#define IPI_PMU_2_IDR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_2_IDR_PL_2_SHIFT   26
#define IPI_PMU_2_IDR_PL_2_WIDTH   1
#define IPI_PMU_2_IDR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_2_IDR_PL_1_SHIFT   25
#define IPI_PMU_2_IDR_PL_1_WIDTH   1
#define IPI_PMU_2_IDR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_2_IDR_PL_0_SHIFT   24
#define IPI_PMU_2_IDR_PL_0_WIDTH   1
#define IPI_PMU_2_IDR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_2_IDR_PMU_3_SHIFT   19
#define IPI_PMU_2_IDR_PMU_3_WIDTH   1
#define IPI_PMU_2_IDR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_2_IDR_PMU_2_SHIFT   18
#define IPI_PMU_2_IDR_PMU_2_WIDTH   1
#define IPI_PMU_2_IDR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_2_IDR_PMU_1_SHIFT   17
#define IPI_PMU_2_IDR_PMU_1_WIDTH   1
#define IPI_PMU_2_IDR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_2_IDR_PMU_0_SHIFT   16
#define IPI_PMU_2_IDR_PMU_0_WIDTH   1
#define IPI_PMU_2_IDR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_2_IDR_RPU_1_SHIFT   9
#define IPI_PMU_2_IDR_RPU_1_WIDTH   1
#define IPI_PMU_2_IDR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_2_IDR_RPU_0_SHIFT   8
#define IPI_PMU_2_IDR_RPU_0_WIDTH   1
#define IPI_PMU_2_IDR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_2_IDR_APU_SHIFT   0
#define IPI_PMU_2_IDR_APU_WIDTH   1
#define IPI_PMU_2_IDR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_3_TRIG
 */
#define IPI_PMU_3_TRIG    ( ( IPI_BASEADDR ) + ((u32)0X00033000U) )

#define IPI_PMU_3_TRIG_PL_3_SHIFT   27
#define IPI_PMU_3_TRIG_PL_3_WIDTH   1
#define IPI_PMU_3_TRIG_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_3_TRIG_PL_2_SHIFT   26
#define IPI_PMU_3_TRIG_PL_2_WIDTH   1
#define IPI_PMU_3_TRIG_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_3_TRIG_PL_1_SHIFT   25
#define IPI_PMU_3_TRIG_PL_1_WIDTH   1
#define IPI_PMU_3_TRIG_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_3_TRIG_PL_0_SHIFT   24
#define IPI_PMU_3_TRIG_PL_0_WIDTH   1
#define IPI_PMU_3_TRIG_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_3_TRIG_PMU_3_SHIFT   19
#define IPI_PMU_3_TRIG_PMU_3_WIDTH   1
#define IPI_PMU_3_TRIG_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_3_TRIG_PMU_2_SHIFT   18
#define IPI_PMU_3_TRIG_PMU_2_WIDTH   1
#define IPI_PMU_3_TRIG_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_3_TRIG_PMU_1_SHIFT   17
#define IPI_PMU_3_TRIG_PMU_1_WIDTH   1
#define IPI_PMU_3_TRIG_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_3_TRIG_PMU_0_SHIFT   16
#define IPI_PMU_3_TRIG_PMU_0_WIDTH   1
#define IPI_PMU_3_TRIG_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_3_TRIG_RPU_1_SHIFT   9
#define IPI_PMU_3_TRIG_RPU_1_WIDTH   1
#define IPI_PMU_3_TRIG_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_3_TRIG_RPU_0_SHIFT   8
#define IPI_PMU_3_TRIG_RPU_0_WIDTH   1
#define IPI_PMU_3_TRIG_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_3_TRIG_APU_SHIFT   0
#define IPI_PMU_3_TRIG_APU_WIDTH   1
#define IPI_PMU_3_TRIG_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_3_OBS
 */
#define IPI_PMU_3_OBS    ( ( IPI_BASEADDR ) + ((u32)0X00033004U) )

#define IPI_PMU_3_OBS_PL_3_SHIFT   27
#define IPI_PMU_3_OBS_PL_3_WIDTH   1
#define IPI_PMU_3_OBS_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_3_OBS_PL_2_SHIFT   26
#define IPI_PMU_3_OBS_PL_2_WIDTH   1
#define IPI_PMU_3_OBS_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_3_OBS_PL_1_SHIFT   25
#define IPI_PMU_3_OBS_PL_1_WIDTH   1
#define IPI_PMU_3_OBS_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_3_OBS_PL_0_SHIFT   24
#define IPI_PMU_3_OBS_PL_0_WIDTH   1
#define IPI_PMU_3_OBS_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_3_OBS_PMU_3_SHIFT   19
#define IPI_PMU_3_OBS_PMU_3_WIDTH   1
#define IPI_PMU_3_OBS_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_3_OBS_PMU_2_SHIFT   18
#define IPI_PMU_3_OBS_PMU_2_WIDTH   1
#define IPI_PMU_3_OBS_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_3_OBS_PMU_1_SHIFT   17
#define IPI_PMU_3_OBS_PMU_1_WIDTH   1
#define IPI_PMU_3_OBS_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_3_OBS_PMU_0_SHIFT   16
#define IPI_PMU_3_OBS_PMU_0_WIDTH   1
#define IPI_PMU_3_OBS_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_3_OBS_RPU_1_SHIFT   9
#define IPI_PMU_3_OBS_RPU_1_WIDTH   1
#define IPI_PMU_3_OBS_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_3_OBS_RPU_0_SHIFT   8
#define IPI_PMU_3_OBS_RPU_0_WIDTH   1
#define IPI_PMU_3_OBS_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_3_OBS_APU_SHIFT   0
#define IPI_PMU_3_OBS_APU_WIDTH   1
#define IPI_PMU_3_OBS_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_3_ISR
 */
#define IPI_PMU_3_ISR    ( ( IPI_BASEADDR ) + ((u32)0X00033010U) )

#define IPI_PMU_3_ISR_PL_3_SHIFT   27
#define IPI_PMU_3_ISR_PL_3_WIDTH   1
#define IPI_PMU_3_ISR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_3_ISR_PL_2_SHIFT   26
#define IPI_PMU_3_ISR_PL_2_WIDTH   1
#define IPI_PMU_3_ISR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_3_ISR_PL_1_SHIFT   25
#define IPI_PMU_3_ISR_PL_1_WIDTH   1
#define IPI_PMU_3_ISR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_3_ISR_PL_0_SHIFT   24
#define IPI_PMU_3_ISR_PL_0_WIDTH   1
#define IPI_PMU_3_ISR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_3_ISR_PMU_3_SHIFT   19
#define IPI_PMU_3_ISR_PMU_3_WIDTH   1
#define IPI_PMU_3_ISR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_3_ISR_PMU_2_SHIFT   18
#define IPI_PMU_3_ISR_PMU_2_WIDTH   1
#define IPI_PMU_3_ISR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_3_ISR_PMU_1_SHIFT   17
#define IPI_PMU_3_ISR_PMU_1_WIDTH   1
#define IPI_PMU_3_ISR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_3_ISR_PMU_0_SHIFT   16
#define IPI_PMU_3_ISR_PMU_0_WIDTH   1
#define IPI_PMU_3_ISR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_3_ISR_RPU_1_SHIFT   9
#define IPI_PMU_3_ISR_RPU_1_WIDTH   1
#define IPI_PMU_3_ISR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_3_ISR_RPU_0_SHIFT   8
#define IPI_PMU_3_ISR_RPU_0_WIDTH   1
#define IPI_PMU_3_ISR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_3_ISR_APU_SHIFT   0
#define IPI_PMU_3_ISR_APU_WIDTH   1
#define IPI_PMU_3_ISR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_3_IMR
 */
#define IPI_PMU_3_IMR    ( ( IPI_BASEADDR ) + ((u32)0X00033014U) )

#define IPI_PMU_3_IMR_PL_3_SHIFT   27
#define IPI_PMU_3_IMR_PL_3_WIDTH   1
#define IPI_PMU_3_IMR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_3_IMR_PL_2_SHIFT   26
#define IPI_PMU_3_IMR_PL_2_WIDTH   1
#define IPI_PMU_3_IMR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_3_IMR_PL_1_SHIFT   25
#define IPI_PMU_3_IMR_PL_1_WIDTH   1
#define IPI_PMU_3_IMR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_3_IMR_PL_0_SHIFT   24
#define IPI_PMU_3_IMR_PL_0_WIDTH   1
#define IPI_PMU_3_IMR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_3_IMR_PMU_3_SHIFT   19
#define IPI_PMU_3_IMR_PMU_3_WIDTH   1
#define IPI_PMU_3_IMR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_3_IMR_PMU_2_SHIFT   18
#define IPI_PMU_3_IMR_PMU_2_WIDTH   1
#define IPI_PMU_3_IMR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_3_IMR_PMU_1_SHIFT   17
#define IPI_PMU_3_IMR_PMU_1_WIDTH   1
#define IPI_PMU_3_IMR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_3_IMR_PMU_0_SHIFT   16
#define IPI_PMU_3_IMR_PMU_0_WIDTH   1
#define IPI_PMU_3_IMR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_3_IMR_RPU_1_SHIFT   9
#define IPI_PMU_3_IMR_RPU_1_WIDTH   1
#define IPI_PMU_3_IMR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_3_IMR_RPU_0_SHIFT   8
#define IPI_PMU_3_IMR_RPU_0_WIDTH   1
#define IPI_PMU_3_IMR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_3_IMR_APU_SHIFT   0
#define IPI_PMU_3_IMR_APU_WIDTH   1
#define IPI_PMU_3_IMR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_3_IER
 */
#define IPI_PMU_3_IER    ( ( IPI_BASEADDR ) + ((u32)0X00033018U) )

#define IPI_PMU_3_IER_PL_3_SHIFT   27
#define IPI_PMU_3_IER_PL_3_WIDTH   1
#define IPI_PMU_3_IER_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_3_IER_PL_2_SHIFT   26
#define IPI_PMU_3_IER_PL_2_WIDTH   1
#define IPI_PMU_3_IER_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_3_IER_PL_1_SHIFT   25
#define IPI_PMU_3_IER_PL_1_WIDTH   1
#define IPI_PMU_3_IER_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_3_IER_PL_0_SHIFT   24
#define IPI_PMU_3_IER_PL_0_WIDTH   1
#define IPI_PMU_3_IER_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_3_IER_PMU_3_SHIFT   19
#define IPI_PMU_3_IER_PMU_3_WIDTH   1
#define IPI_PMU_3_IER_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_3_IER_PMU_2_SHIFT   18
#define IPI_PMU_3_IER_PMU_2_WIDTH   1
#define IPI_PMU_3_IER_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_3_IER_PMU_1_SHIFT   17
#define IPI_PMU_3_IER_PMU_1_WIDTH   1
#define IPI_PMU_3_IER_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_3_IER_PMU_0_SHIFT   16
#define IPI_PMU_3_IER_PMU_0_WIDTH   1
#define IPI_PMU_3_IER_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_3_IER_RPU_1_SHIFT   9
#define IPI_PMU_3_IER_RPU_1_WIDTH   1
#define IPI_PMU_3_IER_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_3_IER_RPU_0_SHIFT   8
#define IPI_PMU_3_IER_RPU_0_WIDTH   1
#define IPI_PMU_3_IER_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_3_IER_APU_SHIFT   0
#define IPI_PMU_3_IER_APU_WIDTH   1
#define IPI_PMU_3_IER_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PMU_3_IDR
 */
#define IPI_PMU_3_IDR    ( ( IPI_BASEADDR ) + ((u32)0X0003301CU) )

#define IPI_PMU_3_IDR_PL_3_SHIFT   27
#define IPI_PMU_3_IDR_PL_3_WIDTH   1
#define IPI_PMU_3_IDR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PMU_3_IDR_PL_2_SHIFT   26
#define IPI_PMU_3_IDR_PL_2_WIDTH   1
#define IPI_PMU_3_IDR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PMU_3_IDR_PL_1_SHIFT   25
#define IPI_PMU_3_IDR_PL_1_WIDTH   1
#define IPI_PMU_3_IDR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PMU_3_IDR_PL_0_SHIFT   24
#define IPI_PMU_3_IDR_PL_0_WIDTH   1
#define IPI_PMU_3_IDR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PMU_3_IDR_PMU_3_SHIFT   19
#define IPI_PMU_3_IDR_PMU_3_WIDTH   1
#define IPI_PMU_3_IDR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PMU_3_IDR_PMU_2_SHIFT   18
#define IPI_PMU_3_IDR_PMU_2_WIDTH   1
#define IPI_PMU_3_IDR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PMU_3_IDR_PMU_1_SHIFT   17
#define IPI_PMU_3_IDR_PMU_1_WIDTH   1
#define IPI_PMU_3_IDR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PMU_3_IDR_PMU_0_SHIFT   16
#define IPI_PMU_3_IDR_PMU_0_WIDTH   1
#define IPI_PMU_3_IDR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PMU_3_IDR_RPU_1_SHIFT   9
#define IPI_PMU_3_IDR_RPU_1_WIDTH   1
#define IPI_PMU_3_IDR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PMU_3_IDR_RPU_0_SHIFT   8
#define IPI_PMU_3_IDR_RPU_0_WIDTH   1
#define IPI_PMU_3_IDR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PMU_3_IDR_APU_SHIFT   0
#define IPI_PMU_3_IDR_APU_WIDTH   1
#define IPI_PMU_3_IDR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_0_TRIG
 */
#define IPI_PL_0_TRIG    ( ( IPI_BASEADDR ) + ((u32)0X00040000U) )

#define IPI_PL_0_TRIG_PL_3_SHIFT   27
#define IPI_PL_0_TRIG_PL_3_WIDTH   1
#define IPI_PL_0_TRIG_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_0_TRIG_PL_2_SHIFT   26
#define IPI_PL_0_TRIG_PL_2_WIDTH   1
#define IPI_PL_0_TRIG_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_0_TRIG_PL_1_SHIFT   25
#define IPI_PL_0_TRIG_PL_1_WIDTH   1
#define IPI_PL_0_TRIG_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_0_TRIG_PL_0_SHIFT   24
#define IPI_PL_0_TRIG_PL_0_WIDTH   1
#define IPI_PL_0_TRIG_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_0_TRIG_PMU_3_SHIFT   19
#define IPI_PL_0_TRIG_PMU_3_WIDTH   1
#define IPI_PL_0_TRIG_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_0_TRIG_PMU_2_SHIFT   18
#define IPI_PL_0_TRIG_PMU_2_WIDTH   1
#define IPI_PL_0_TRIG_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_0_TRIG_PMU_1_SHIFT   17
#define IPI_PL_0_TRIG_PMU_1_WIDTH   1
#define IPI_PL_0_TRIG_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_0_TRIG_PMU_0_SHIFT   16
#define IPI_PL_0_TRIG_PMU_0_WIDTH   1
#define IPI_PL_0_TRIG_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_0_TRIG_RPU_1_SHIFT   9
#define IPI_PL_0_TRIG_RPU_1_WIDTH   1
#define IPI_PL_0_TRIG_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_0_TRIG_RPU_0_SHIFT   8
#define IPI_PL_0_TRIG_RPU_0_WIDTH   1
#define IPI_PL_0_TRIG_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_0_TRIG_APU_SHIFT   0
#define IPI_PL_0_TRIG_APU_WIDTH   1
#define IPI_PL_0_TRIG_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_0_OBS
 */
#define IPI_PL_0_OBS    ( ( IPI_BASEADDR ) + ((u32)0X00040004U) )

#define IPI_PL_0_OBS_PL_3_SHIFT   27
#define IPI_PL_0_OBS_PL_3_WIDTH   1
#define IPI_PL_0_OBS_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_0_OBS_PL_2_SHIFT   26
#define IPI_PL_0_OBS_PL_2_WIDTH   1
#define IPI_PL_0_OBS_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_0_OBS_PL_1_SHIFT   25
#define IPI_PL_0_OBS_PL_1_WIDTH   1
#define IPI_PL_0_OBS_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_0_OBS_PL_0_SHIFT   24
#define IPI_PL_0_OBS_PL_0_WIDTH   1
#define IPI_PL_0_OBS_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_0_OBS_PMU_3_SHIFT   19
#define IPI_PL_0_OBS_PMU_3_WIDTH   1
#define IPI_PL_0_OBS_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_0_OBS_PMU_2_SHIFT   18
#define IPI_PL_0_OBS_PMU_2_WIDTH   1
#define IPI_PL_0_OBS_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_0_OBS_PMU_1_SHIFT   17
#define IPI_PL_0_OBS_PMU_1_WIDTH   1
#define IPI_PL_0_OBS_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_0_OBS_PMU_0_SHIFT   16
#define IPI_PL_0_OBS_PMU_0_WIDTH   1
#define IPI_PL_0_OBS_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_0_OBS_RPU_1_SHIFT   9
#define IPI_PL_0_OBS_RPU_1_WIDTH   1
#define IPI_PL_0_OBS_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_0_OBS_RPU_0_SHIFT   8
#define IPI_PL_0_OBS_RPU_0_WIDTH   1
#define IPI_PL_0_OBS_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_0_OBS_APU_SHIFT   0
#define IPI_PL_0_OBS_APU_WIDTH   1
#define IPI_PL_0_OBS_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_0_ISR
 */
#define IPI_PL_0_ISR    ( ( IPI_BASEADDR ) + ((u32)0X00040010U) )

#define IPI_PL_0_ISR_PL_3_SHIFT   27
#define IPI_PL_0_ISR_PL_3_WIDTH   1
#define IPI_PL_0_ISR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_0_ISR_PL_2_SHIFT   26
#define IPI_PL_0_ISR_PL_2_WIDTH   1
#define IPI_PL_0_ISR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_0_ISR_PL_1_SHIFT   25
#define IPI_PL_0_ISR_PL_1_WIDTH   1
#define IPI_PL_0_ISR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_0_ISR_PL_0_SHIFT   24
#define IPI_PL_0_ISR_PL_0_WIDTH   1
#define IPI_PL_0_ISR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_0_ISR_PMU_3_SHIFT   19
#define IPI_PL_0_ISR_PMU_3_WIDTH   1
#define IPI_PL_0_ISR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_0_ISR_PMU_2_SHIFT   18
#define IPI_PL_0_ISR_PMU_2_WIDTH   1
#define IPI_PL_0_ISR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_0_ISR_PMU_1_SHIFT   17
#define IPI_PL_0_ISR_PMU_1_WIDTH   1
#define IPI_PL_0_ISR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_0_ISR_PMU_0_SHIFT   16
#define IPI_PL_0_ISR_PMU_0_WIDTH   1
#define IPI_PL_0_ISR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_0_ISR_RPU_1_SHIFT   9
#define IPI_PL_0_ISR_RPU_1_WIDTH   1
#define IPI_PL_0_ISR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_0_ISR_RPU_0_SHIFT   8
#define IPI_PL_0_ISR_RPU_0_WIDTH   1
#define IPI_PL_0_ISR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_0_ISR_APU_SHIFT   0
#define IPI_PL_0_ISR_APU_WIDTH   1
#define IPI_PL_0_ISR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_0_IMR
 */
#define IPI_PL_0_IMR    ( ( IPI_BASEADDR ) + ((u32)0X00040014U) )

#define IPI_PL_0_IMR_PL_3_SHIFT   27
#define IPI_PL_0_IMR_PL_3_WIDTH   1
#define IPI_PL_0_IMR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_0_IMR_PL_2_SHIFT   26
#define IPI_PL_0_IMR_PL_2_WIDTH   1
#define IPI_PL_0_IMR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_0_IMR_PL_1_SHIFT   25
#define IPI_PL_0_IMR_PL_1_WIDTH   1
#define IPI_PL_0_IMR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_0_IMR_PL_0_SHIFT   24
#define IPI_PL_0_IMR_PL_0_WIDTH   1
#define IPI_PL_0_IMR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_0_IMR_PMU_3_SHIFT   19
#define IPI_PL_0_IMR_PMU_3_WIDTH   1
#define IPI_PL_0_IMR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_0_IMR_PMU_2_SHIFT   18
#define IPI_PL_0_IMR_PMU_2_WIDTH   1
#define IPI_PL_0_IMR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_0_IMR_PMU_1_SHIFT   17
#define IPI_PL_0_IMR_PMU_1_WIDTH   1
#define IPI_PL_0_IMR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_0_IMR_PMU_0_SHIFT   16
#define IPI_PL_0_IMR_PMU_0_WIDTH   1
#define IPI_PL_0_IMR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_0_IMR_RPU_1_SHIFT   9
#define IPI_PL_0_IMR_RPU_1_WIDTH   1
#define IPI_PL_0_IMR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_0_IMR_RPU_0_SHIFT   8
#define IPI_PL_0_IMR_RPU_0_WIDTH   1
#define IPI_PL_0_IMR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_0_IMR_APU_SHIFT   0
#define IPI_PL_0_IMR_APU_WIDTH   1
#define IPI_PL_0_IMR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_0_IER
 */
#define IPI_PL_0_IER    ( ( IPI_BASEADDR ) + ((u32)0X00040018U) )

#define IPI_PL_0_IER_PL_3_SHIFT   27
#define IPI_PL_0_IER_PL_3_WIDTH   1
#define IPI_PL_0_IER_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_0_IER_PL_2_SHIFT   26
#define IPI_PL_0_IER_PL_2_WIDTH   1
#define IPI_PL_0_IER_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_0_IER_PL_1_SHIFT   25
#define IPI_PL_0_IER_PL_1_WIDTH   1
#define IPI_PL_0_IER_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_0_IER_PL_0_SHIFT   24
#define IPI_PL_0_IER_PL_0_WIDTH   1
#define IPI_PL_0_IER_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_0_IER_PMU_3_SHIFT   19
#define IPI_PL_0_IER_PMU_3_WIDTH   1
#define IPI_PL_0_IER_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_0_IER_PMU_2_SHIFT   18
#define IPI_PL_0_IER_PMU_2_WIDTH   1
#define IPI_PL_0_IER_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_0_IER_PMU_1_SHIFT   17
#define IPI_PL_0_IER_PMU_1_WIDTH   1
#define IPI_PL_0_IER_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_0_IER_PMU_0_SHIFT   16
#define IPI_PL_0_IER_PMU_0_WIDTH   1
#define IPI_PL_0_IER_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_0_IER_RPU_1_SHIFT   9
#define IPI_PL_0_IER_RPU_1_WIDTH   1
#define IPI_PL_0_IER_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_0_IER_RPU_0_SHIFT   8
#define IPI_PL_0_IER_RPU_0_WIDTH   1
#define IPI_PL_0_IER_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_0_IER_APU_SHIFT   0
#define IPI_PL_0_IER_APU_WIDTH   1
#define IPI_PL_0_IER_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_0_IDR
 */
#define IPI_PL_0_IDR    ( ( IPI_BASEADDR ) + ((u32)0X0004001CU) )

#define IPI_PL_0_IDR_PL_3_SHIFT   27
#define IPI_PL_0_IDR_PL_3_WIDTH   1
#define IPI_PL_0_IDR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_0_IDR_PL_2_SHIFT   26
#define IPI_PL_0_IDR_PL_2_WIDTH   1
#define IPI_PL_0_IDR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_0_IDR_PL_1_SHIFT   25
#define IPI_PL_0_IDR_PL_1_WIDTH   1
#define IPI_PL_0_IDR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_0_IDR_PL_0_SHIFT   24
#define IPI_PL_0_IDR_PL_0_WIDTH   1
#define IPI_PL_0_IDR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_0_IDR_PMU_3_SHIFT   19
#define IPI_PL_0_IDR_PMU_3_WIDTH   1
#define IPI_PL_0_IDR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_0_IDR_PMU_2_SHIFT   18
#define IPI_PL_0_IDR_PMU_2_WIDTH   1
#define IPI_PL_0_IDR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_0_IDR_PMU_1_SHIFT   17
#define IPI_PL_0_IDR_PMU_1_WIDTH   1
#define IPI_PL_0_IDR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_0_IDR_PMU_0_SHIFT   16
#define IPI_PL_0_IDR_PMU_0_WIDTH   1
#define IPI_PL_0_IDR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_0_IDR_RPU_1_SHIFT   9
#define IPI_PL_0_IDR_RPU_1_WIDTH   1
#define IPI_PL_0_IDR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_0_IDR_RPU_0_SHIFT   8
#define IPI_PL_0_IDR_RPU_0_WIDTH   1
#define IPI_PL_0_IDR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_0_IDR_APU_SHIFT   0
#define IPI_PL_0_IDR_APU_WIDTH   1
#define IPI_PL_0_IDR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_1_TRIG
 */
#define IPI_PL_1_TRIG    ( ( IPI_BASEADDR ) + ((u32)0X00050000U) )

#define IPI_PL_1_TRIG_PL_3_SHIFT   27
#define IPI_PL_1_TRIG_PL_3_WIDTH   1
#define IPI_PL_1_TRIG_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_1_TRIG_PL_2_SHIFT   26
#define IPI_PL_1_TRIG_PL_2_WIDTH   1
#define IPI_PL_1_TRIG_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_1_TRIG_PL_1_SHIFT   25
#define IPI_PL_1_TRIG_PL_1_WIDTH   1
#define IPI_PL_1_TRIG_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_1_TRIG_PL_0_SHIFT   24
#define IPI_PL_1_TRIG_PL_0_WIDTH   1
#define IPI_PL_1_TRIG_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_1_TRIG_PMU_3_SHIFT   19
#define IPI_PL_1_TRIG_PMU_3_WIDTH   1
#define IPI_PL_1_TRIG_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_1_TRIG_PMU_2_SHIFT   18
#define IPI_PL_1_TRIG_PMU_2_WIDTH   1
#define IPI_PL_1_TRIG_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_1_TRIG_PMU_1_SHIFT   17
#define IPI_PL_1_TRIG_PMU_1_WIDTH   1
#define IPI_PL_1_TRIG_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_1_TRIG_PMU_0_SHIFT   16
#define IPI_PL_1_TRIG_PMU_0_WIDTH   1
#define IPI_PL_1_TRIG_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_1_TRIG_RPU_1_SHIFT   9
#define IPI_PL_1_TRIG_RPU_1_WIDTH   1
#define IPI_PL_1_TRIG_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_1_TRIG_RPU_0_SHIFT   8
#define IPI_PL_1_TRIG_RPU_0_WIDTH   1
#define IPI_PL_1_TRIG_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_1_TRIG_APU_SHIFT   0
#define IPI_PL_1_TRIG_APU_WIDTH   1
#define IPI_PL_1_TRIG_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_1_OBS
 */
#define IPI_PL_1_OBS    ( ( IPI_BASEADDR ) + ((u32)0X00050004U) )

#define IPI_PL_1_OBS_PL_3_SHIFT   27
#define IPI_PL_1_OBS_PL_3_WIDTH   1
#define IPI_PL_1_OBS_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_1_OBS_PL_2_SHIFT   26
#define IPI_PL_1_OBS_PL_2_WIDTH   1
#define IPI_PL_1_OBS_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_1_OBS_PL_1_SHIFT   25
#define IPI_PL_1_OBS_PL_1_WIDTH   1
#define IPI_PL_1_OBS_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_1_OBS_PL_0_SHIFT   24
#define IPI_PL_1_OBS_PL_0_WIDTH   1
#define IPI_PL_1_OBS_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_1_OBS_PMU_3_SHIFT   19
#define IPI_PL_1_OBS_PMU_3_WIDTH   1
#define IPI_PL_1_OBS_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_1_OBS_PMU_2_SHIFT   18
#define IPI_PL_1_OBS_PMU_2_WIDTH   1
#define IPI_PL_1_OBS_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_1_OBS_PMU_1_SHIFT   17
#define IPI_PL_1_OBS_PMU_1_WIDTH   1
#define IPI_PL_1_OBS_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_1_OBS_PMU_0_SHIFT   16
#define IPI_PL_1_OBS_PMU_0_WIDTH   1
#define IPI_PL_1_OBS_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_1_OBS_RPU_1_SHIFT   9
#define IPI_PL_1_OBS_RPU_1_WIDTH   1
#define IPI_PL_1_OBS_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_1_OBS_RPU_0_SHIFT   8
#define IPI_PL_1_OBS_RPU_0_WIDTH   1
#define IPI_PL_1_OBS_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_1_OBS_APU_SHIFT   0
#define IPI_PL_1_OBS_APU_WIDTH   1
#define IPI_PL_1_OBS_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_1_ISR
 */
#define IPI_PL_1_ISR    ( ( IPI_BASEADDR ) + ((u32)0X00050010U) )

#define IPI_PL_1_ISR_PL_3_SHIFT   27
#define IPI_PL_1_ISR_PL_3_WIDTH   1
#define IPI_PL_1_ISR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_1_ISR_PL_2_SHIFT   26
#define IPI_PL_1_ISR_PL_2_WIDTH   1
#define IPI_PL_1_ISR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_1_ISR_PL_1_SHIFT   25
#define IPI_PL_1_ISR_PL_1_WIDTH   1
#define IPI_PL_1_ISR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_1_ISR_PL_0_SHIFT   24
#define IPI_PL_1_ISR_PL_0_WIDTH   1
#define IPI_PL_1_ISR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_1_ISR_PMU_3_SHIFT   19
#define IPI_PL_1_ISR_PMU_3_WIDTH   1
#define IPI_PL_1_ISR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_1_ISR_PMU_2_SHIFT   18
#define IPI_PL_1_ISR_PMU_2_WIDTH   1
#define IPI_PL_1_ISR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_1_ISR_PMU_1_SHIFT   17
#define IPI_PL_1_ISR_PMU_1_WIDTH   1
#define IPI_PL_1_ISR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_1_ISR_PMU_0_SHIFT   16
#define IPI_PL_1_ISR_PMU_0_WIDTH   1
#define IPI_PL_1_ISR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_1_ISR_RPU_1_SHIFT   9
#define IPI_PL_1_ISR_RPU_1_WIDTH   1
#define IPI_PL_1_ISR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_1_ISR_RPU_0_SHIFT   8
#define IPI_PL_1_ISR_RPU_0_WIDTH   1
#define IPI_PL_1_ISR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_1_ISR_APU_SHIFT   0
#define IPI_PL_1_ISR_APU_WIDTH   1
#define IPI_PL_1_ISR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_1_IMR
 */
#define IPI_PL_1_IMR    ( ( IPI_BASEADDR ) + ((u32)0X00050014U) )

#define IPI_PL_1_IMR_PL_3_SHIFT   27
#define IPI_PL_1_IMR_PL_3_WIDTH   1
#define IPI_PL_1_IMR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_1_IMR_PL_2_SHIFT   26
#define IPI_PL_1_IMR_PL_2_WIDTH   1
#define IPI_PL_1_IMR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_1_IMR_PL_1_SHIFT   25
#define IPI_PL_1_IMR_PL_1_WIDTH   1
#define IPI_PL_1_IMR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_1_IMR_PL_0_SHIFT   24
#define IPI_PL_1_IMR_PL_0_WIDTH   1
#define IPI_PL_1_IMR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_1_IMR_PMU_3_SHIFT   19
#define IPI_PL_1_IMR_PMU_3_WIDTH   1
#define IPI_PL_1_IMR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_1_IMR_PMU_2_SHIFT   18
#define IPI_PL_1_IMR_PMU_2_WIDTH   1
#define IPI_PL_1_IMR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_1_IMR_PMU_1_SHIFT   17
#define IPI_PL_1_IMR_PMU_1_WIDTH   1
#define IPI_PL_1_IMR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_1_IMR_PMU_0_SHIFT   16
#define IPI_PL_1_IMR_PMU_0_WIDTH   1
#define IPI_PL_1_IMR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_1_IMR_RPU_1_SHIFT   9
#define IPI_PL_1_IMR_RPU_1_WIDTH   1
#define IPI_PL_1_IMR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_1_IMR_RPU_0_SHIFT   8
#define IPI_PL_1_IMR_RPU_0_WIDTH   1
#define IPI_PL_1_IMR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_1_IMR_APU_SHIFT   0
#define IPI_PL_1_IMR_APU_WIDTH   1
#define IPI_PL_1_IMR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_1_IER
 */
#define IPI_PL_1_IER    ( ( IPI_BASEADDR ) + ((u32)0X00050018U) )

#define IPI_PL_1_IER_PL_3_SHIFT   27
#define IPI_PL_1_IER_PL_3_WIDTH   1
#define IPI_PL_1_IER_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_1_IER_PL_2_SHIFT   26
#define IPI_PL_1_IER_PL_2_WIDTH   1
#define IPI_PL_1_IER_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_1_IER_PL_1_SHIFT   25
#define IPI_PL_1_IER_PL_1_WIDTH   1
#define IPI_PL_1_IER_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_1_IER_PL_0_SHIFT   24
#define IPI_PL_1_IER_PL_0_WIDTH   1
#define IPI_PL_1_IER_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_1_IER_PMU_3_SHIFT   19
#define IPI_PL_1_IER_PMU_3_WIDTH   1
#define IPI_PL_1_IER_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_1_IER_PMU_2_SHIFT   18
#define IPI_PL_1_IER_PMU_2_WIDTH   1
#define IPI_PL_1_IER_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_1_IER_PMU_1_SHIFT   17
#define IPI_PL_1_IER_PMU_1_WIDTH   1
#define IPI_PL_1_IER_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_1_IER_PMU_0_SHIFT   16
#define IPI_PL_1_IER_PMU_0_WIDTH   1
#define IPI_PL_1_IER_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_1_IER_RPU_1_SHIFT   9
#define IPI_PL_1_IER_RPU_1_WIDTH   1
#define IPI_PL_1_IER_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_1_IER_RPU_0_SHIFT   8
#define IPI_PL_1_IER_RPU_0_WIDTH   1
#define IPI_PL_1_IER_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_1_IER_APU_SHIFT   0
#define IPI_PL_1_IER_APU_WIDTH   1
#define IPI_PL_1_IER_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_1_IDR
 */
#define IPI_PL_1_IDR    ( ( IPI_BASEADDR ) + ((u32)0X0005001CU) )

#define IPI_PL_1_IDR_PL_3_SHIFT   27
#define IPI_PL_1_IDR_PL_3_WIDTH   1
#define IPI_PL_1_IDR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_1_IDR_PL_2_SHIFT   26
#define IPI_PL_1_IDR_PL_2_WIDTH   1
#define IPI_PL_1_IDR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_1_IDR_PL_1_SHIFT   25
#define IPI_PL_1_IDR_PL_1_WIDTH   1
#define IPI_PL_1_IDR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_1_IDR_PL_0_SHIFT   24
#define IPI_PL_1_IDR_PL_0_WIDTH   1
#define IPI_PL_1_IDR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_1_IDR_PMU_3_SHIFT   19
#define IPI_PL_1_IDR_PMU_3_WIDTH   1
#define IPI_PL_1_IDR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_1_IDR_PMU_2_SHIFT   18
#define IPI_PL_1_IDR_PMU_2_WIDTH   1
#define IPI_PL_1_IDR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_1_IDR_PMU_1_SHIFT   17
#define IPI_PL_1_IDR_PMU_1_WIDTH   1
#define IPI_PL_1_IDR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_1_IDR_PMU_0_SHIFT   16
#define IPI_PL_1_IDR_PMU_0_WIDTH   1
#define IPI_PL_1_IDR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_1_IDR_RPU_1_SHIFT   9
#define IPI_PL_1_IDR_RPU_1_WIDTH   1
#define IPI_PL_1_IDR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_1_IDR_RPU_0_SHIFT   8
#define IPI_PL_1_IDR_RPU_0_WIDTH   1
#define IPI_PL_1_IDR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_1_IDR_APU_SHIFT   0
#define IPI_PL_1_IDR_APU_WIDTH   1
#define IPI_PL_1_IDR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_2_TRIG
 */
#define IPI_PL_2_TRIG    ( ( IPI_BASEADDR ) + ((u32)0X00060000U) )

#define IPI_PL_2_TRIG_PL_3_SHIFT   27
#define IPI_PL_2_TRIG_PL_3_WIDTH   1
#define IPI_PL_2_TRIG_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_2_TRIG_PL_2_SHIFT   26
#define IPI_PL_2_TRIG_PL_2_WIDTH   1
#define IPI_PL_2_TRIG_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_2_TRIG_PL_1_SHIFT   25
#define IPI_PL_2_TRIG_PL_1_WIDTH   1
#define IPI_PL_2_TRIG_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_2_TRIG_PL_0_SHIFT   24
#define IPI_PL_2_TRIG_PL_0_WIDTH   1
#define IPI_PL_2_TRIG_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_2_TRIG_PMU_3_SHIFT   19
#define IPI_PL_2_TRIG_PMU_3_WIDTH   1
#define IPI_PL_2_TRIG_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_2_TRIG_PMU_2_SHIFT   18
#define IPI_PL_2_TRIG_PMU_2_WIDTH   1
#define IPI_PL_2_TRIG_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_2_TRIG_PMU_1_SHIFT   17
#define IPI_PL_2_TRIG_PMU_1_WIDTH   1
#define IPI_PL_2_TRIG_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_2_TRIG_PMU_0_SHIFT   16
#define IPI_PL_2_TRIG_PMU_0_WIDTH   1
#define IPI_PL_2_TRIG_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_2_TRIG_RPU_1_SHIFT   9
#define IPI_PL_2_TRIG_RPU_1_WIDTH   1
#define IPI_PL_2_TRIG_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_2_TRIG_RPU_0_SHIFT   8
#define IPI_PL_2_TRIG_RPU_0_WIDTH   1
#define IPI_PL_2_TRIG_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_2_TRIG_APU_SHIFT   0
#define IPI_PL_2_TRIG_APU_WIDTH   1
#define IPI_PL_2_TRIG_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_2_OBS
 */
#define IPI_PL_2_OBS    ( ( IPI_BASEADDR ) + ((u32)0X00060004U) )

#define IPI_PL_2_OBS_PL_3_SHIFT   27
#define IPI_PL_2_OBS_PL_3_WIDTH   1
#define IPI_PL_2_OBS_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_2_OBS_PL_2_SHIFT   26
#define IPI_PL_2_OBS_PL_2_WIDTH   1
#define IPI_PL_2_OBS_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_2_OBS_PL_1_SHIFT   25
#define IPI_PL_2_OBS_PL_1_WIDTH   1
#define IPI_PL_2_OBS_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_2_OBS_PL_0_SHIFT   24
#define IPI_PL_2_OBS_PL_0_WIDTH   1
#define IPI_PL_2_OBS_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_2_OBS_PMU_3_SHIFT   19
#define IPI_PL_2_OBS_PMU_3_WIDTH   1
#define IPI_PL_2_OBS_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_2_OBS_PMU_2_SHIFT   18
#define IPI_PL_2_OBS_PMU_2_WIDTH   1
#define IPI_PL_2_OBS_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_2_OBS_PMU_1_SHIFT   17
#define IPI_PL_2_OBS_PMU_1_WIDTH   1
#define IPI_PL_2_OBS_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_2_OBS_PMU_0_SHIFT   16
#define IPI_PL_2_OBS_PMU_0_WIDTH   1
#define IPI_PL_2_OBS_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_2_OBS_RPU_1_SHIFT   9
#define IPI_PL_2_OBS_RPU_1_WIDTH   1
#define IPI_PL_2_OBS_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_2_OBS_RPU_0_SHIFT   8
#define IPI_PL_2_OBS_RPU_0_WIDTH   1
#define IPI_PL_2_OBS_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_2_OBS_APU_SHIFT   0
#define IPI_PL_2_OBS_APU_WIDTH   1
#define IPI_PL_2_OBS_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_2_ISR
 */
#define IPI_PL_2_ISR    ( ( IPI_BASEADDR ) + ((u32)0X00060010U) )

#define IPI_PL_2_ISR_PL_3_SHIFT   27
#define IPI_PL_2_ISR_PL_3_WIDTH   1
#define IPI_PL_2_ISR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_2_ISR_PL_2_SHIFT   26
#define IPI_PL_2_ISR_PL_2_WIDTH   1
#define IPI_PL_2_ISR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_2_ISR_PL_1_SHIFT   25
#define IPI_PL_2_ISR_PL_1_WIDTH   1
#define IPI_PL_2_ISR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_2_ISR_PL_0_SHIFT   24
#define IPI_PL_2_ISR_PL_0_WIDTH   1
#define IPI_PL_2_ISR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_2_ISR_PMU_3_SHIFT   19
#define IPI_PL_2_ISR_PMU_3_WIDTH   1
#define IPI_PL_2_ISR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_2_ISR_PMU_2_SHIFT   18
#define IPI_PL_2_ISR_PMU_2_WIDTH   1
#define IPI_PL_2_ISR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_2_ISR_PMU_1_SHIFT   17
#define IPI_PL_2_ISR_PMU_1_WIDTH   1
#define IPI_PL_2_ISR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_2_ISR_PMU_0_SHIFT   16
#define IPI_PL_2_ISR_PMU_0_WIDTH   1
#define IPI_PL_2_ISR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_2_ISR_RPU_1_SHIFT   9
#define IPI_PL_2_ISR_RPU_1_WIDTH   1
#define IPI_PL_2_ISR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_2_ISR_RPU_0_SHIFT   8
#define IPI_PL_2_ISR_RPU_0_WIDTH   1
#define IPI_PL_2_ISR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_2_ISR_APU_SHIFT   0
#define IPI_PL_2_ISR_APU_WIDTH   1
#define IPI_PL_2_ISR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_2_IMR
 */
#define IPI_PL_2_IMR    ( ( IPI_BASEADDR ) + ((u32)0X00060014U) )

#define IPI_PL_2_IMR_PL_3_SHIFT   27
#define IPI_PL_2_IMR_PL_3_WIDTH   1
#define IPI_PL_2_IMR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_2_IMR_PL_2_SHIFT   26
#define IPI_PL_2_IMR_PL_2_WIDTH   1
#define IPI_PL_2_IMR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_2_IMR_PL_1_SHIFT   25
#define IPI_PL_2_IMR_PL_1_WIDTH   1
#define IPI_PL_2_IMR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_2_IMR_PL_0_SHIFT   24
#define IPI_PL_2_IMR_PL_0_WIDTH   1
#define IPI_PL_2_IMR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_2_IMR_PMU_3_SHIFT   19
#define IPI_PL_2_IMR_PMU_3_WIDTH   1
#define IPI_PL_2_IMR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_2_IMR_PMU_2_SHIFT   18
#define IPI_PL_2_IMR_PMU_2_WIDTH   1
#define IPI_PL_2_IMR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_2_IMR_PMU_1_SHIFT   17
#define IPI_PL_2_IMR_PMU_1_WIDTH   1
#define IPI_PL_2_IMR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_2_IMR_PMU_0_SHIFT   16
#define IPI_PL_2_IMR_PMU_0_WIDTH   1
#define IPI_PL_2_IMR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_2_IMR_RPU_1_SHIFT   9
#define IPI_PL_2_IMR_RPU_1_WIDTH   1
#define IPI_PL_2_IMR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_2_IMR_RPU_0_SHIFT   8
#define IPI_PL_2_IMR_RPU_0_WIDTH   1
#define IPI_PL_2_IMR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_2_IMR_APU_SHIFT   0
#define IPI_PL_2_IMR_APU_WIDTH   1
#define IPI_PL_2_IMR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_2_IER
 */
#define IPI_PL_2_IER    ( ( IPI_BASEADDR ) + ((u32)0X00060018U) )

#define IPI_PL_2_IER_PL_3_SHIFT   27
#define IPI_PL_2_IER_PL_3_WIDTH   1
#define IPI_PL_2_IER_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_2_IER_PL_2_SHIFT   26
#define IPI_PL_2_IER_PL_2_WIDTH   1
#define IPI_PL_2_IER_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_2_IER_PL_1_SHIFT   25
#define IPI_PL_2_IER_PL_1_WIDTH   1
#define IPI_PL_2_IER_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_2_IER_PL_0_SHIFT   24
#define IPI_PL_2_IER_PL_0_WIDTH   1
#define IPI_PL_2_IER_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_2_IER_PMU_3_SHIFT   19
#define IPI_PL_2_IER_PMU_3_WIDTH   1
#define IPI_PL_2_IER_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_2_IER_PMU_2_SHIFT   18
#define IPI_PL_2_IER_PMU_2_WIDTH   1
#define IPI_PL_2_IER_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_2_IER_PMU_1_SHIFT   17
#define IPI_PL_2_IER_PMU_1_WIDTH   1
#define IPI_PL_2_IER_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_2_IER_PMU_0_SHIFT   16
#define IPI_PL_2_IER_PMU_0_WIDTH   1
#define IPI_PL_2_IER_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_2_IER_RPU_1_SHIFT   9
#define IPI_PL_2_IER_RPU_1_WIDTH   1
#define IPI_PL_2_IER_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_2_IER_RPU_0_SHIFT   8
#define IPI_PL_2_IER_RPU_0_WIDTH   1
#define IPI_PL_2_IER_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_2_IER_APU_SHIFT   0
#define IPI_PL_2_IER_APU_WIDTH   1
#define IPI_PL_2_IER_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_2_IDR
 */
#define IPI_PL_2_IDR    ( ( IPI_BASEADDR ) + ((u32)0X0006001CU) )

#define IPI_PL_2_IDR_PL_3_SHIFT   27
#define IPI_PL_2_IDR_PL_3_WIDTH   1
#define IPI_PL_2_IDR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_2_IDR_PL_2_SHIFT   26
#define IPI_PL_2_IDR_PL_2_WIDTH   1
#define IPI_PL_2_IDR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_2_IDR_PL_1_SHIFT   25
#define IPI_PL_2_IDR_PL_1_WIDTH   1
#define IPI_PL_2_IDR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_2_IDR_PL_0_SHIFT   24
#define IPI_PL_2_IDR_PL_0_WIDTH   1
#define IPI_PL_2_IDR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_2_IDR_PMU_3_SHIFT   19
#define IPI_PL_2_IDR_PMU_3_WIDTH   1
#define IPI_PL_2_IDR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_2_IDR_PMU_2_SHIFT   18
#define IPI_PL_2_IDR_PMU_2_WIDTH   1
#define IPI_PL_2_IDR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_2_IDR_PMU_1_SHIFT   17
#define IPI_PL_2_IDR_PMU_1_WIDTH   1
#define IPI_PL_2_IDR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_2_IDR_PMU_0_SHIFT   16
#define IPI_PL_2_IDR_PMU_0_WIDTH   1
#define IPI_PL_2_IDR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_2_IDR_RPU_1_SHIFT   9
#define IPI_PL_2_IDR_RPU_1_WIDTH   1
#define IPI_PL_2_IDR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_2_IDR_RPU_0_SHIFT   8
#define IPI_PL_2_IDR_RPU_0_WIDTH   1
#define IPI_PL_2_IDR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_2_IDR_APU_SHIFT   0
#define IPI_PL_2_IDR_APU_WIDTH   1
#define IPI_PL_2_IDR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_3_TRIG
 */
#define IPI_PL_3_TRIG    ( ( IPI_BASEADDR ) + ((u32)0X00070000U) )

#define IPI_PL_3_TRIG_PL_3_SHIFT   27
#define IPI_PL_3_TRIG_PL_3_WIDTH   1
#define IPI_PL_3_TRIG_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_3_TRIG_PL_2_SHIFT   26
#define IPI_PL_3_TRIG_PL_2_WIDTH   1
#define IPI_PL_3_TRIG_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_3_TRIG_PL_1_SHIFT   25
#define IPI_PL_3_TRIG_PL_1_WIDTH   1
#define IPI_PL_3_TRIG_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_3_TRIG_PL_0_SHIFT   24
#define IPI_PL_3_TRIG_PL_0_WIDTH   1
#define IPI_PL_3_TRIG_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_3_TRIG_PMU_3_SHIFT   19
#define IPI_PL_3_TRIG_PMU_3_WIDTH   1
#define IPI_PL_3_TRIG_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_3_TRIG_PMU_2_SHIFT   18
#define IPI_PL_3_TRIG_PMU_2_WIDTH   1
#define IPI_PL_3_TRIG_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_3_TRIG_PMU_1_SHIFT   17
#define IPI_PL_3_TRIG_PMU_1_WIDTH   1
#define IPI_PL_3_TRIG_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_3_TRIG_PMU_0_SHIFT   16
#define IPI_PL_3_TRIG_PMU_0_WIDTH   1
#define IPI_PL_3_TRIG_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_3_TRIG_RPU_1_SHIFT   9
#define IPI_PL_3_TRIG_RPU_1_WIDTH   1
#define IPI_PL_3_TRIG_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_3_TRIG_RPU_0_SHIFT   8
#define IPI_PL_3_TRIG_RPU_0_WIDTH   1
#define IPI_PL_3_TRIG_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_3_TRIG_APU_SHIFT   0
#define IPI_PL_3_TRIG_APU_WIDTH   1
#define IPI_PL_3_TRIG_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_3_OBS
 */
#define IPI_PL_3_OBS    ( ( IPI_BASEADDR ) + ((u32)0X00070004U) )

#define IPI_PL_3_OBS_PL_3_SHIFT   27
#define IPI_PL_3_OBS_PL_3_WIDTH   1
#define IPI_PL_3_OBS_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_3_OBS_PL_2_SHIFT   26
#define IPI_PL_3_OBS_PL_2_WIDTH   1
#define IPI_PL_3_OBS_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_3_OBS_PL_1_SHIFT   25
#define IPI_PL_3_OBS_PL_1_WIDTH   1
#define IPI_PL_3_OBS_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_3_OBS_PL_0_SHIFT   24
#define IPI_PL_3_OBS_PL_0_WIDTH   1
#define IPI_PL_3_OBS_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_3_OBS_PMU_3_SHIFT   19
#define IPI_PL_3_OBS_PMU_3_WIDTH   1
#define IPI_PL_3_OBS_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_3_OBS_PMU_2_SHIFT   18
#define IPI_PL_3_OBS_PMU_2_WIDTH   1
#define IPI_PL_3_OBS_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_3_OBS_PMU_1_SHIFT   17
#define IPI_PL_3_OBS_PMU_1_WIDTH   1
#define IPI_PL_3_OBS_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_3_OBS_PMU_0_SHIFT   16
#define IPI_PL_3_OBS_PMU_0_WIDTH   1
#define IPI_PL_3_OBS_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_3_OBS_RPU_1_SHIFT   9
#define IPI_PL_3_OBS_RPU_1_WIDTH   1
#define IPI_PL_3_OBS_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_3_OBS_RPU_0_SHIFT   8
#define IPI_PL_3_OBS_RPU_0_WIDTH   1
#define IPI_PL_3_OBS_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_3_OBS_APU_SHIFT   0
#define IPI_PL_3_OBS_APU_WIDTH   1
#define IPI_PL_3_OBS_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_3_ISR
 */
#define IPI_PL_3_ISR    ( ( IPI_BASEADDR ) + ((u32)0X00070010U) )

#define IPI_PL_3_ISR_PL_3_SHIFT   27
#define IPI_PL_3_ISR_PL_3_WIDTH   1
#define IPI_PL_3_ISR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_3_ISR_PL_2_SHIFT   26
#define IPI_PL_3_ISR_PL_2_WIDTH   1
#define IPI_PL_3_ISR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_3_ISR_PL_1_SHIFT   25
#define IPI_PL_3_ISR_PL_1_WIDTH   1
#define IPI_PL_3_ISR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_3_ISR_PL_0_SHIFT   24
#define IPI_PL_3_ISR_PL_0_WIDTH   1
#define IPI_PL_3_ISR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_3_ISR_PMU_3_SHIFT   19
#define IPI_PL_3_ISR_PMU_3_WIDTH   1
#define IPI_PL_3_ISR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_3_ISR_PMU_2_SHIFT   18
#define IPI_PL_3_ISR_PMU_2_WIDTH   1
#define IPI_PL_3_ISR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_3_ISR_PMU_1_SHIFT   17
#define IPI_PL_3_ISR_PMU_1_WIDTH   1
#define IPI_PL_3_ISR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_3_ISR_PMU_0_SHIFT   16
#define IPI_PL_3_ISR_PMU_0_WIDTH   1
#define IPI_PL_3_ISR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_3_ISR_RPU_1_SHIFT   9
#define IPI_PL_3_ISR_RPU_1_WIDTH   1
#define IPI_PL_3_ISR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_3_ISR_RPU_0_SHIFT   8
#define IPI_PL_3_ISR_RPU_0_WIDTH   1
#define IPI_PL_3_ISR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_3_ISR_APU_SHIFT   0
#define IPI_PL_3_ISR_APU_WIDTH   1
#define IPI_PL_3_ISR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_3_IMR
 */
#define IPI_PL_3_IMR    ( ( IPI_BASEADDR ) + ((u32)0X00070014U) )

#define IPI_PL_3_IMR_PL_3_SHIFT   27
#define IPI_PL_3_IMR_PL_3_WIDTH   1
#define IPI_PL_3_IMR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_3_IMR_PL_2_SHIFT   26
#define IPI_PL_3_IMR_PL_2_WIDTH   1
#define IPI_PL_3_IMR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_3_IMR_PL_1_SHIFT   25
#define IPI_PL_3_IMR_PL_1_WIDTH   1
#define IPI_PL_3_IMR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_3_IMR_PL_0_SHIFT   24
#define IPI_PL_3_IMR_PL_0_WIDTH   1
#define IPI_PL_3_IMR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_3_IMR_PMU_3_SHIFT   19
#define IPI_PL_3_IMR_PMU_3_WIDTH   1
#define IPI_PL_3_IMR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_3_IMR_PMU_2_SHIFT   18
#define IPI_PL_3_IMR_PMU_2_WIDTH   1
#define IPI_PL_3_IMR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_3_IMR_PMU_1_SHIFT   17
#define IPI_PL_3_IMR_PMU_1_WIDTH   1
#define IPI_PL_3_IMR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_3_IMR_PMU_0_SHIFT   16
#define IPI_PL_3_IMR_PMU_0_WIDTH   1
#define IPI_PL_3_IMR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_3_IMR_RPU_1_SHIFT   9
#define IPI_PL_3_IMR_RPU_1_WIDTH   1
#define IPI_PL_3_IMR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_3_IMR_RPU_0_SHIFT   8
#define IPI_PL_3_IMR_RPU_0_WIDTH   1
#define IPI_PL_3_IMR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_3_IMR_APU_SHIFT   0
#define IPI_PL_3_IMR_APU_WIDTH   1
#define IPI_PL_3_IMR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_3_IER
 */
#define IPI_PL_3_IER    ( ( IPI_BASEADDR ) + ((u32)0X00070018U) )

#define IPI_PL_3_IER_PL_3_SHIFT   27
#define IPI_PL_3_IER_PL_3_WIDTH   1
#define IPI_PL_3_IER_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_3_IER_PL_2_SHIFT   26
#define IPI_PL_3_IER_PL_2_WIDTH   1
#define IPI_PL_3_IER_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_3_IER_PL_1_SHIFT   25
#define IPI_PL_3_IER_PL_1_WIDTH   1
#define IPI_PL_3_IER_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_3_IER_PL_0_SHIFT   24
#define IPI_PL_3_IER_PL_0_WIDTH   1
#define IPI_PL_3_IER_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_3_IER_PMU_3_SHIFT   19
#define IPI_PL_3_IER_PMU_3_WIDTH   1
#define IPI_PL_3_IER_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_3_IER_PMU_2_SHIFT   18
#define IPI_PL_3_IER_PMU_2_WIDTH   1
#define IPI_PL_3_IER_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_3_IER_PMU_1_SHIFT   17
#define IPI_PL_3_IER_PMU_1_WIDTH   1
#define IPI_PL_3_IER_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_3_IER_PMU_0_SHIFT   16
#define IPI_PL_3_IER_PMU_0_WIDTH   1
#define IPI_PL_3_IER_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_3_IER_RPU_1_SHIFT   9
#define IPI_PL_3_IER_RPU_1_WIDTH   1
#define IPI_PL_3_IER_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_3_IER_RPU_0_SHIFT   8
#define IPI_PL_3_IER_RPU_0_WIDTH   1
#define IPI_PL_3_IER_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_3_IER_APU_SHIFT   0
#define IPI_PL_3_IER_APU_WIDTH   1
#define IPI_PL_3_IER_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_PL_3_IDR
 */
#define IPI_PL_3_IDR    ( ( IPI_BASEADDR ) + ((u32)0X0007001CU) )

#define IPI_PL_3_IDR_PL_3_SHIFT   27
#define IPI_PL_3_IDR_PL_3_WIDTH   1
#define IPI_PL_3_IDR_PL_3_MASK    ((u32)0X08000000U)

#define IPI_PL_3_IDR_PL_2_SHIFT   26
#define IPI_PL_3_IDR_PL_2_WIDTH   1
#define IPI_PL_3_IDR_PL_2_MASK    ((u32)0X04000000U)

#define IPI_PL_3_IDR_PL_1_SHIFT   25
#define IPI_PL_3_IDR_PL_1_WIDTH   1
#define IPI_PL_3_IDR_PL_1_MASK    ((u32)0X02000000U)

#define IPI_PL_3_IDR_PL_0_SHIFT   24
#define IPI_PL_3_IDR_PL_0_WIDTH   1
#define IPI_PL_3_IDR_PL_0_MASK    ((u32)0X01000000U)

#define IPI_PL_3_IDR_PMU_3_SHIFT   19
#define IPI_PL_3_IDR_PMU_3_WIDTH   1
#define IPI_PL_3_IDR_PMU_3_MASK    ((u32)0X00080000U)

#define IPI_PL_3_IDR_PMU_2_SHIFT   18
#define IPI_PL_3_IDR_PMU_2_WIDTH   1
#define IPI_PL_3_IDR_PMU_2_MASK    ((u32)0X00040000U)

#define IPI_PL_3_IDR_PMU_1_SHIFT   17
#define IPI_PL_3_IDR_PMU_1_WIDTH   1
#define IPI_PL_3_IDR_PMU_1_MASK    ((u32)0X00020000U)

#define IPI_PL_3_IDR_PMU_0_SHIFT   16
#define IPI_PL_3_IDR_PMU_0_WIDTH   1
#define IPI_PL_3_IDR_PMU_0_MASK    ((u32)0X00010000U)

#define IPI_PL_3_IDR_RPU_1_SHIFT   9
#define IPI_PL_3_IDR_RPU_1_WIDTH   1
#define IPI_PL_3_IDR_RPU_1_MASK    ((u32)0X00000200U)

#define IPI_PL_3_IDR_RPU_0_SHIFT   8
#define IPI_PL_3_IDR_RPU_0_WIDTH   1
#define IPI_PL_3_IDR_RPU_0_MASK    ((u32)0X00000100U)

#define IPI_PL_3_IDR_APU_SHIFT   0
#define IPI_PL_3_IDR_APU_WIDTH   1
#define IPI_PL_3_IDR_APU_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_IPI_CTRL
 */
#define IPI_IPI_CTRL    ( ( IPI_BASEADDR ) + ((u32)0X00080000U) )

#define IPI_IPI_CTRL_SLVERR_ENABLE_SHIFT   0
#define IPI_IPI_CTRL_SLVERR_ENABLE_WIDTH   1
#define IPI_IPI_CTRL_SLVERR_ENABLE_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_IPI_ISR
 */
#define IPI_IPI_ISR    ( ( IPI_BASEADDR ) + ((u32)0X00080010U) )

#define IPI_IPI_ISR_ADDR_DECODE_ERR_SHIFT   0
#define IPI_IPI_ISR_ADDR_DECODE_ERR_WIDTH   1
#define IPI_IPI_ISR_ADDR_DECODE_ERR_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_IPI_IMR
 */
#define IPI_IPI_IMR    ( ( IPI_BASEADDR ) + ((u32)0X00080014U) )

#define IPI_IPI_IMR_ADDR_DECODE_ERR_SHIFT   0
#define IPI_IPI_IMR_ADDR_DECODE_ERR_WIDTH   1
#define IPI_IPI_IMR_ADDR_DECODE_ERR_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_IPI_IER
 */
#define IPI_IPI_IER    ( ( IPI_BASEADDR ) + ((u32)0X00080018U) )

#define IPI_IPI_IER_ADDR_DECODE_ERR_SHIFT   0
#define IPI_IPI_IER_ADDR_DECODE_ERR_WIDTH   1
#define IPI_IPI_IER_ADDR_DECODE_ERR_MASK    ((u32)0X00000001U)

/**
 * Register: IPI_IPI_ECO
 */
#define IPI_IPI_ECO    ( ( IPI_BASEADDR ) + ((u32)0X00080020U) )

#define IPI_IPI_ECO_ECO_SHIFT   0
#define IPI_IPI_ECO_ECO_WIDTH   32
#define IPI_IPI_ECO_ECO_MASK    ((u32)0XFFFFFFFFU)

/**
 * Register: IPI_SAFETY_CHK
 */
#define IPI_SAFETY_CHK    ( ( IPI_BASEADDR ) + ((u32)0X00080030U) )

#define IPI_SAFETY_CHK_DATA_SHIFT   0
#define IPI_SAFETY_CHK_DATA_WIDTH   32
#define IPI_SAFETY_CHK_DATA_MASK    ((u32)0XFFFFFFFFU)

/**
 * Register: IPI_IPI_IDR
 */
#define IPI_IPI_IDR    ( ( IPI_BASEADDR ) + ((u32)0X000C001CU) )

#define IPI_IPI_IDR_ADDR_DECODE_ERR_SHIFT   0
#define IPI_IPI_IDR_ADDR_DECODE_ERR_WIDTH   1
#define IPI_IPI_IDR_ADDR_DECODE_ERR_MASK    ((u32)0X00000001U)

#ifdef __cplusplus
}
#endif


#endif /* _IPI_H_ */
